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[u-boot,0/1] aspeed: msx4: switch phy-mode to rgmii-id

Message ID 20260504044702.2613879-1-andhsieh@nvidia.com
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Series aspeed: msx4: switch phy-mode to rgmii-id | expand

Message

Ender Hsieh May 4, 2026, 4:47 a.m. UTC 
Following Aspeed (Jacky Chou) and Andrew Lunn's guidance on
linux-aspeed [1], switch the MSX4 board to phy-mode = "rgmii-id"
so the PHY handles internal RX/TX delay, and remove the SCU
mac0-clk-delay block since SoC-side delay is no longer needed.

A coordinated kernel-side change adding the &mac0/&mdio3 nodes
with phy-mode = "rgmii-id" to aspeed-bmc-nvidia-msx4-bmc.dts will
be sent to mainline Linux separately.

Tested on alon8 hardware: 1G link negotiation succeeds with this
change in coordination with the kernel-side patch.

[1] https://lore.kernel.org/linux-aspeed/eac09481-0ba1-4ac2-ad8c-d859822ff0d5@lunn.ch/

Ender Hsieh (1):
  ARM: dts: ast2600 msx4: switch to rgmii-id phy mode

 arch/arm/dts/ast2600-msx4-bmc-nvidia.dts | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)