From patchwork Sat Mar 21 20:59:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Cochran X-Patchwork-Id: 453033 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 97E23140146 for ; Sun, 22 Mar 2015 08:04:39 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="verification failed; unprotected key" header.d=gmail.com header.i=@gmail.com header.b=CJ2zz/Ca; dkim-adsp=none (unprotected policy); dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751965AbbCUVAa (ORCPT ); Sat, 21 Mar 2015 17:00:30 -0400 Received: from mail-we0-f181.google.com ([74.125.82.181]:33089 "EHLO mail-we0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751944AbbCUVA0 (ORCPT ); Sat, 21 Mar 2015 17:00:26 -0400 Received: by weop45 with SMTP id p45so107628525weo.0; Sat, 21 Mar 2015 14:00:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j03wiRtIkLVmN4MEwKp8OBUzFGqi2EjRvNc6ps6heKQ=; b=CJ2zz/CasEE7QQ0ihLHeoEipqQ8xV8pBMSQwRCyzpp/39V0OrHMz7O9dJYN3tZTHMi LsDFBeZc6sB+ap44CVfKTTGYAt42wJh/tFuPsbwLxJeHUg3prWnt4QLXmrECwGCq4Uhj 8MeXiS89JXgIL0xclulFGp34eORz03r/MW0MYWaXVRlmhMVyHoWho5y6LNkcippRBlhY mm3m4wMXcB0RwCW8fU3xN44zn14fUBWa0lc6oo7lrzWe41Oi5UNJbmxjSc6COMPgXS+T jhmPNl9kQolX2y0HBmVDREpFW+VdHUk7vN7pPNNmRI5FAXAXwB1TKqMe5PR+I93Pr5JY AYrQ== X-Received: by 10.194.157.68 with SMTP id wk4mr52355653wjb.130.1426971624598; Sat, 21 Mar 2015 14:00:24 -0700 (PDT) Received: from hoboy.home (194-96-185-227.adsl.highway.telekom.at. [194.96.185.227]) by mx.google.com with ESMTPSA id dn7sm3916401wid.12.2015.03.21.14.00.22 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 21 Mar 2015 14:00:23 -0700 (PDT) From: Richard Cochran To: Cc: , Amir Vadai , Ariel Elior , Arnd Bergmann , Baolin Wang , Ben Hutchings , Bruce Allan , Carolyn Wyborny , Chris Metcalf , David Miller , Frank Li , Giuseppe Cavallaro , Jeff Kirsher , John Stultz , Luwei Zhou , Matthew Vick , Michael Chan , Prashant Sreedharan , Shradha Shah , Solarflare linux maintainers , Sonic Zhang , =?UTF-8?q?Stefan=20S=C3=B8rensen?= , Thomas Gleixner , Tom Lendacky Subject: [RFC net-next 11/22] ptp: i40e: convert to the 64 bit get/set time methods. Date: Sat, 21 Mar 2015 21:59:41 +0100 Message-Id: X-Mailer: git-send-email 1.7.10.4 In-Reply-To: References: Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The device appears to use a 64 bit nanoseconds register, and so with this patch the driver should be ready for the year 2038. Compile tested only. Signed-off-by: Richard Cochran --- drivers/net/ethernet/intel/i40e/i40e_ptp.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_ptp.c b/drivers/net/ethernet/intel/i40e/i40e_ptp.c index fabcfa1..a92b772 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_ptp.c +++ b/drivers/net/ethernet/intel/i40e/i40e_ptp.c @@ -57,7 +57,7 @@ * timespec. However, since the registers are 64 bits of nanoseconds, we must * convert the result to a timespec before we can return. **/ -static void i40e_ptp_read(struct i40e_pf *pf, struct timespec *ts) +static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts) { struct i40e_hw *hw = &pf->hw; u32 hi, lo; @@ -69,7 +69,7 @@ static void i40e_ptp_read(struct i40e_pf *pf, struct timespec *ts) ns = (((u64)hi) << 32) | lo; - *ts = ns_to_timespec(ns); + *ts = ns_to_timespec64(ns); } /** @@ -81,10 +81,10 @@ static void i40e_ptp_read(struct i40e_pf *pf, struct timespec *ts) * we receive a timespec from the stack, we must convert that timespec into * nanoseconds before programming the registers. **/ -static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec *ts) +static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts) { struct i40e_hw *hw = &pf->hw; - u64 ns = timespec_to_ns(ts); + u64 ns = timespec64_to_ns(ts); /* The timer will not update until the high register is written, so * write the low register first. @@ -159,14 +159,14 @@ static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) { struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); - struct timespec now, then = ns_to_timespec(delta); + struct timespec64 now, then = ns_to_timespec64(delta); unsigned long flags; spin_lock_irqsave(&pf->tmreg_lock, flags); i40e_ptp_read(pf, &now); - now = timespec_add(now, then); - i40e_ptp_write(pf, (const struct timespec *)&now); + now = timespec64_add(now, then); + i40e_ptp_write(pf, (const struct timespec64 *)&now); spin_unlock_irqrestore(&pf->tmreg_lock, flags); @@ -181,7 +181,7 @@ static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) * Read the device clock and return the correct value on ns, after converting it * into a timespec struct. **/ -static int i40e_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts) +static int i40e_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) { struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); unsigned long flags; @@ -202,7 +202,7 @@ static int i40e_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts) * to ns happens in the write function. **/ static int i40e_ptp_settime(struct ptp_clock_info *ptp, - const struct timespec *ts) + const struct timespec64 *ts) { struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps); unsigned long flags; @@ -613,8 +613,8 @@ static long i40e_ptp_create_clock(struct i40e_pf *pf) pf->ptp_caps.pps = 0; pf->ptp_caps.adjfreq = i40e_ptp_adjfreq; pf->ptp_caps.adjtime = i40e_ptp_adjtime; - pf->ptp_caps.gettime = i40e_ptp_gettime; - pf->ptp_caps.settime = i40e_ptp_settime; + pf->ptp_caps.gettime64 = i40e_ptp_gettime; + pf->ptp_caps.settime64 = i40e_ptp_settime; pf->ptp_caps.enable = i40e_ptp_feature_enable; /* Attempt to register the clock before enabling the hardware. */ @@ -673,7 +673,7 @@ void i40e_ptp_init(struct i40e_pf *pf) dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n", __func__); } else { - struct timespec ts; + struct timespec64 ts; u32 regval; dev_info(&pf->pdev->dev, "%s: added PHC on %s\n", __func__, @@ -695,7 +695,7 @@ void i40e_ptp_init(struct i40e_pf *pf) i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config); /* Set the clock value. */ - ts = ktime_to_timespec(ktime_get_real()); + ts = ktime_to_timespec64(ktime_get_real()); i40e_ptp_settime(&pf->ptp_caps, &ts); } }