Message ID | aed891fb-8568-2291-6050-18b6e2fd12e8@gmail.com |
---|---|
State | Accepted |
Delegated to: | David Miller |
Headers | show |
Series | [net-next] net: dsa: mv88e6xxx: SERDES support 2500BaseT via external PHY | expand |
From: Heiner Kallweit <hkallweit1@gmail.com> Date: Fri, 8 Feb 2019 22:25:44 +0100 > From: Andrew Lunn <andrew@lunn.ch> > By using an external PHY, ports 9 and 10 can support 2500BaseT. > So set this link mode in the mask when validating. > > Signed-off-by: Andrew Lunn <andrew@lunn.ch> > Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Applied.
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 8dca2c949..739c0c168 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -647,8 +647,10 @@ static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, unsigned long *mask, struct phylink_link_state *state) { - if (port >= 9) + if (port >= 9) { phylink_set(mask, 2500baseX_Full); + phylink_set(mask, 2500baseT_Full); + } /* No ethtool bits for 200Mbps */ phylink_set(mask, 1000baseT_Full);