diff mbox series

[net-next] net: phy: mscc: add constants for used interrupt mask bits

Message ID 6503f7cf-477d-954b-ab7c-c9805cfa3692@gmail.com
State Accepted
Delegated to: David Miller
Headers show
Series [net-next] net: phy: mscc: add constants for used interrupt mask bits | expand

Commit Message

Heiner Kallweit March 1, 2020, 8:57 p.m. UTC
Add constants for the used interrupts bits. This avoids the magic
number for MII_VSC85XX_INT_MASK_MASK.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
---
 drivers/net/phy/mscc.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

Comments

Andrew Lunn March 1, 2020, 9:40 p.m. UTC | #1
On Sun, Mar 01, 2020 at 09:57:08PM +0100, Heiner Kallweit wrote:
> Add constants for the used interrupts bits. This avoids the magic
> number for MII_VSC85XX_INT_MASK_MASK.
> 
> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew
David Miller March 2, 2020, 3:06 a.m. UTC | #2
From: Heiner Kallweit <hkallweit1@gmail.com>
Date: Sun, 1 Mar 2020 21:57:08 +0100

> Add constants for the used interrupts bits. This avoids the magic
> number for MII_VSC85XX_INT_MASK_MASK.
> 
> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>

Applied to net-next.
diff mbox series

Patch

diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c
index 8b1535c4d..32b551cbb 100644
--- a/drivers/net/phy/mscc.c
+++ b/drivers/net/phy/mscc.c
@@ -80,10 +80,16 @@  enum rgmii_rx_clock_delay {
 #define MSCC_PHY_EXT_PHY_CNTL_2		  24
 
 #define MII_VSC85XX_INT_MASK		  25
-#define MII_VSC85XX_INT_MASK_MASK	  0xa020
-#define MII_VSC85XX_INT_MASK_WOL	  0x0040
+#define MII_VSC85XX_INT_MASK_MDINT	  BIT(15)
+#define MII_VSC85XX_INT_MASK_LINK_CHG	  BIT(13)
+#define MII_VSC85XX_INT_MASK_WOL	  BIT(6)
+#define MII_VSC85XX_INT_MASK_EXT	  BIT(5)
 #define MII_VSC85XX_INT_STATUS		  26
 
+#define MII_VSC85XX_INT_MASK_MASK	  (MII_VSC85XX_INT_MASK_MDINT    | \
+					   MII_VSC85XX_INT_MASK_LINK_CHG | \
+					   MII_VSC85XX_INT_MASK_EXT)
+
 #define MSCC_PHY_WOL_MAC_CONTROL          27
 #define EDGE_RATE_CNTL_POS                5
 #define EDGE_RATE_CNTL_MASK               0x00E0