| Message ID | 20200904131247.23021-1-wanghai38@huawei.com |
|---|---|
| State | Awaiting Upstream |
| Delegated to: | David Miller |
| Headers | show |
| Series | [net-next] can: peak_canfd: Remove unused macros | expand |
On 9/4/20 3:12 PM, Wang Hai wrote: > CANFD_CLK_SEL_DIV_MASK and CANFD_OPTIONS_SET are > never used after they were introduced. Remove them. > > Reported-by: Hulk Robot <hulkci@huawei.com> > Signed-off-by: Wang Hai <wanghai38@huawei.com> > --- > drivers/net/can/peak_canfd/peak_pciefd_main.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/drivers/net/can/peak_canfd/peak_pciefd_main.c b/drivers/net/can/peak_canfd/peak_pciefd_main.c > index 9469d4421afe..5f0f39d2fa28 100644 > --- a/drivers/net/can/peak_canfd/peak_pciefd_main.c > +++ b/drivers/net/can/peak_canfd/peak_pciefd_main.c > @@ -83,7 +83,6 @@ MODULE_LICENSE("GPL v2"); > #define CANFD_MISC_TS_RST 0x00000001 /* timestamp cnt rst */ > > /* CAN-FD channel Clock SELector Source & DIVider */ > -#define CANFD_CLK_SEL_DIV_MASK 0x00000007 I would like to keep this for documentation purpose. > #define CANFD_CLK_SEL_DIV_60MHZ 0x00000000 /* SRC=240MHz only */ > #define CANFD_CLK_SEL_DIV_40MHZ 0x00000001 /* SRC=240MHz only */ > #define CANFD_CLK_SEL_DIV_30MHZ 0x00000002 /* SRC=240MHz only */ > @@ -116,8 +115,6 @@ MODULE_LICENSE("GPL v2"); > #define CANFD_CTL_IRQ_CL_DEF 16 /* Rx msg max nb per IRQ in Rx DMA */ > #define CANFD_CTL_IRQ_TL_DEF 10 /* Time before IRQ if < CL (x100 µs) */ > > -#define CANFD_OPTIONS_SET (CANFD_OPTION_ERROR | CANFD_OPTION_BUSLOAD) > - Okay, let's remove this. > /* Tx anticipation window (link logical address should be aligned on 2K > * boundary) > */ > Marc
diff --git a/drivers/net/can/peak_canfd/peak_pciefd_main.c b/drivers/net/can/peak_canfd/peak_pciefd_main.c index 9469d4421afe..5f0f39d2fa28 100644 --- a/drivers/net/can/peak_canfd/peak_pciefd_main.c +++ b/drivers/net/can/peak_canfd/peak_pciefd_main.c @@ -83,7 +83,6 @@ MODULE_LICENSE("GPL v2"); #define CANFD_MISC_TS_RST 0x00000001 /* timestamp cnt rst */ /* CAN-FD channel Clock SELector Source & DIVider */ -#define CANFD_CLK_SEL_DIV_MASK 0x00000007 #define CANFD_CLK_SEL_DIV_60MHZ 0x00000000 /* SRC=240MHz only */ #define CANFD_CLK_SEL_DIV_40MHZ 0x00000001 /* SRC=240MHz only */ #define CANFD_CLK_SEL_DIV_30MHZ 0x00000002 /* SRC=240MHz only */ @@ -116,8 +115,6 @@ MODULE_LICENSE("GPL v2"); #define CANFD_CTL_IRQ_CL_DEF 16 /* Rx msg max nb per IRQ in Rx DMA */ #define CANFD_CTL_IRQ_TL_DEF 10 /* Time before IRQ if < CL (x100 µs) */ -#define CANFD_OPTIONS_SET (CANFD_OPTION_ERROR | CANFD_OPTION_BUSLOAD) - /* Tx anticipation window (link logical address should be aligned on 2K * boundary) */
CANFD_CLK_SEL_DIV_MASK and CANFD_OPTIONS_SET are never used after they were introduced. Remove them. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wang Hai <wanghai38@huawei.com> --- drivers/net/can/peak_canfd/peak_pciefd_main.c | 3 --- 1 file changed, 3 deletions(-)