From patchwork Sun May 28 00:34:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jakub Kicinski X-Patchwork-Id: 767817 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wb19x6L7jz9s2G for ; Sun, 28 May 2017 10:35:33 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=netronome-com.20150623.gappssmtp.com header.i=@netronome-com.20150623.gappssmtp.com header.b="NV4UQ39v"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750950AbdE1AfY (ORCPT ); Sat, 27 May 2017 20:35:24 -0400 Received: from mail-pf0-f181.google.com ([209.85.192.181]:34470 "EHLO mail-pf0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750784AbdE1Aep (ORCPT ); Sat, 27 May 2017 20:34:45 -0400 Received: by mail-pf0-f181.google.com with SMTP id 9so32597449pfj.1 for ; Sat, 27 May 2017 17:34:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=netronome-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Boa8U6xWFWO7JdTtBqLDLhAn3Rh7VHg+wBkS2L2wgF0=; b=NV4UQ39vRkLXaZlUfmGxsK00czBLtuVLE03EETllrXDao/p3jRxnFwJesq9UV5NfT3 gjhxIOIAHPkqtjkvyrhHsJYWFlgkTOjWbZL6dmNVOs2PX+eATRnCnhea+gXKHrFaNpvB NWDJJJFUz39FrHH5PgoYSJTJL0sPj2f14KfU09Tx9dYsyR8xqwMIdniogtyOzSUqprqR EeSYd3rV9lfd6iFzWxR5gSM0uzwcpzNUSuAVH6lqWUyjIov6fWN3tCDNEK2/MEC/zPV5 U9Wr8my3Ovr4YJsL8ajfvtqEgrKAqjyNFJK07XBm8fN5/CLR7cEkF7bWXtBHj7b7hZmH 4/KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Boa8U6xWFWO7JdTtBqLDLhAn3Rh7VHg+wBkS2L2wgF0=; b=sKTsRCA3TDVtfVt30YLFjPulBsRKtillj8TIJKzczmEU/1Ico8T/iiVva281GCwP/s 6Zh7wSuCdmVvIVUThO/OXAWjJFrayG94+vMeo104xFOnXhEK7tcya5OX/8pIDU5RDGFw EzbQ101uqdhvmOtubni2MmMctLZnZ8olbcXpf0i6OXWHxYtwB7ZHVN2Co2guvsV/PkBe T4FPLoC9mEvi4ZKxetWeTySM7OOZgtp0rULik0Ky1BZe+hn5ziXGJaA8uR1XlQkpJnVc bcmDiy4RPJ4MLyKuDJKdfG2LoiwzXNASKpFBt4WKpkafBGlVV6N5qvJ6jyKgM4qd7SEY gtdg== X-Gm-Message-State: AODbwcBfN9bLzFYxHW45xnx6gDbasWW1QOEX10BC+Si/+iFV1Nus+Esi QXOxSpXa7+N1ZZA0NEk= X-Received: by 10.98.29.79 with SMTP id d76mr10307210pfd.141.1495931684821; Sat, 27 May 2017 17:34:44 -0700 (PDT) Received: from jkicinski-Precision-T1700.netronome.com ([75.53.12.129]) by smtp.gmail.com with ESMTPSA id o76sm12119757pfi.119.2017.05.27.17.34.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 27 May 2017 17:34:44 -0700 (PDT) From: Jakub Kicinski To: netdev@vger.kernel.org Cc: oss-drivers@netronome.com, Jakub Kicinski Subject: [PATCH net-next 04/12] nfp: only try to get to PCIe ctrl memory if BARs are wide enough Date: Sat, 27 May 2017 17:34:03 -0700 Message-Id: <20170528003411.17603-5-jakub.kicinski@netronome.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170528003411.17603-1-jakub.kicinski@netronome.com> References: <20170528003411.17603-1-jakub.kicinski@netronome.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org For accessing PCIe ctrl memory we depend on the BAR aperture being large enough to reach all registers. Since the BAR aperture can be set in the flash make sure the driver won't oops the kernel when the PCIe configuration is unusual. Signed-off-by: Jakub Kicinski --- drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c b/drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c index 1fde213d5b83..597ac8febb63 100644 --- a/drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c +++ b/drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c @@ -119,6 +119,11 @@ #define NFP_PCIE_EM 0x020000 #define NFP_PCIE_SRAM 0x000000 +/* Minimal size of the PCIe cfg memory we depend on being mapped, + * queue controller and DMA controller don't have to be covered. + */ +#define NFP_PCI_MIN_MAP_SIZE 0x080000 + #define NFP_PCIE_P2C_FIXED_SIZE(bar) (1 << (bar)->bitsize) #define NFP_PCIE_P2C_BULK_SIZE(bar) (1 << (bar)->bitsize) #define NFP_PCIE_P2C_GENERAL_TARGET_OFFSET(bar, x) ((x) << ((bar)->bitsize - 2)) @@ -628,8 +633,9 @@ static int enable_bars(struct nfp6000_pcie *nfp, u16 interface) /* Configure, and lock, BAR0.0 for General Target use (MSI-X SRAM) */ bar = &nfp->bar[0]; - bar->iomem = ioremap_nocache(nfp_bar_resource_start(bar), - nfp_bar_resource_len(bar)); + if (nfp_bar_resource_len(bar) >= NFP_PCI_MIN_MAP_SIZE) + bar->iomem = ioremap_nocache(nfp_bar_resource_start(bar), + nfp_bar_resource_len(bar)); if (bar->iomem) { dev_info(nfp->dev, "BAR0.0 RESERVED: General Mapping/MSI-X SRAM\n");