| Message ID | 1556126241-2774-2-git-send-email-weifeng.voon@intel.com |
|---|---|
| State | Changes Requested |
| Delegated to: | David Miller |
| Headers | show |
| Series | net: stmmac: enable EHL SGMII | expand |
> Added EHL SGMII 1Gbps PCI ID. Different MII and speed will have different > PCI ID. > For EHL, default TX and RX FIFO size is set to 32KB. This is because the FIFO > size advertised in the HW features is not the same as the HW > implementation. The TX FIFO is shared among all all the TX queues and the > RX FIFO is also shared among all the RX queues. > > Signed-off-by: Weifeng Voon <weifeng.voon@intel.com> > --- > drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 103 > +++++++++++++++++++++++ > 1 file changed, 103 insertions(+) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c > b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c > index d819e8e..b454a97 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c > @@ -118,6 +118,107 @@ static int stmmac_default_data(struct pci_dev > *pdev, > .setup = stmmac_default_data, > }; > > +static int ehl_common_data(struct pci_dev *pdev, > + struct plat_stmmacenet_data *plat) { > + int i; > + > + plat->bus_id = 1; > + plat->phy_addr = 0; > + plat->clk_csr = 5; > + plat->has_gmac = 0; > + plat->has_gmac4 = 1; > + plat->force_sf_dma_mode = 0; > + plat->tso_en = 1; > + > + plat->rx_queues_to_use = 8; > + plat->tx_queues_to_use = 8; > + plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; > + > + for (i = 0; i < plat->rx_queues_to_use; i++) { > + plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; > + plat->rx_queues_cfg[i].chan = i; > + > + /* Disable Priority config by default */ > + plat->tx_queues_cfg[i].use_prio = false; > + > + /* Disable RX queues routing by default */ > + plat->rx_queues_cfg[i].pkt_route = 0x0; > + } > + > + for (i = 0; i < plat->tx_queues_to_use; i++) { > + plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; > + > + /* Disable Priority config by default */ > + plat->tx_queues_cfg[i].use_prio = false; > + } > + > + plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; > + plat->tx_queues_cfg[0].weight = 0x09; > + plat->tx_queues_cfg[1].weight = 0x0A; > + plat->tx_queues_cfg[2].weight = 0x0B; > + plat->tx_queues_cfg[3].weight = 0x0C; > + plat->tx_queues_cfg[4].weight = 0x0D; > + plat->tx_queues_cfg[5].weight = 0x0E; > + plat->tx_queues_cfg[6].weight = 0x0F; > + plat->tx_queues_cfg[7].weight = 0x10; > + > + plat->mdio_bus_data->phy_reset = NULL; > + plat->mdio_bus_data->phy_mask = 0; > + > + plat->dma_cfg->pbl = 32; > + plat->dma_cfg->pblx8 = true; > + plat->dma_cfg->fixed_burst = 0; > + plat->dma_cfg->mixed_burst = 0; > + plat->dma_cfg->aal = 0; > + > + plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), > + GFP_KERNEL); > + if (!plat->axi) > + return -ENOMEM; > + plat->axi->axi_lpi_en = 0; > + plat->axi->axi_xit_frm = 0; > + plat->axi->axi_wr_osr_lmt = 0; > + plat->axi->axi_rd_osr_lmt = 2; > + plat->axi->axi_blen[0] = 4; > + plat->axi->axi_blen[1] = 8; > + plat->axi->axi_blen[2] = 16; > + > + /* Set default value for multicast hash bins */ > + plat->multicast_filter_bins = HASH_TABLE_SIZE; > + > + /* Set default value for unicast filter entries */ > + plat->unicast_filter_entries = 1; > + > + /* Set the maxmtu to a default of JUMBO_LEN */ > + plat->maxmtu = JUMBO_LEN; > + > + plat->tx_fifo_size = 32768; > + plat->rx_fifo_size = 32768; > + > + return 0; > +} > + > +static int ehl_sgmii1g_data(struct pci_dev *pdev, > + struct plat_stmmacenet_data *plat) { > + int ret; > + > + /* Set common default data first */ > + ret = ehl_common_data(pdev, plat); > + > + if (ret) > + return ret; > + > + plat->interface = PHY_INTERFACE_MODE_SGMII; > + > + return 0; > +} > + > +static struct stmmac_pci_info ehl_sgmii1g_pci_info = { > + .setup = ehl_sgmii1g_data, > +}; > + > static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { > { > .func = 6, > @@ -355,6 +456,7 @@ static int __maybe_unused > stmmac_pci_resume(struct device *dev) > > #define STMMAC_QUARK_ID 0x0937 > #define STMMAC_DEVICE_ID 0x1108 > +#define STMMAC_EHL_SGMII1G_ID 0x4b31 > > #define STMMAC_DEVICE(vendor_id, dev_id, info) { \ > PCI_VDEVICE(vendor_id, dev_id), \ > @@ -365,6 +467,7 @@ static int __maybe_unused > stmmac_pci_resume(struct device *dev) > STMMAC_DEVICE(STMMAC, STMMAC_DEVICE_ID, > stmmac_pci_info), > STMMAC_DEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_MAC, > stmmac_pci_info), > STMMAC_DEVICE(INTEL, STMMAC_QUARK_ID, quark_pci_info), > + STMMAC_DEVICE(INTEL, STMMAC_EHL_SGMII1G_ID, > ehl_sgmii1g_pci_info), > {} > }; > > -- > 1.9.1 ++ stmmac maintainers and c45 experts
> ++ stmmac maintainers and c45 experts
Normally you would repost the series as a v2, rather the additional
maintainers added. Please try to remember that for next time.
Andrew
> > ++ stmmac maintainers and c45 experts > > Normally you would repost the series as a v2, rather the additional > maintainers added. Please try to remember that for next time. Noted and I will remember that. The reason I did not repost the series as v2 is because v1 is still in discussion and I am not changing any code besides adding additional maintainers. Thanks. Weifeng > > Andrew
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c index d819e8e..b454a97 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c @@ -118,6 +118,107 @@ static int stmmac_default_data(struct pci_dev *pdev, .setup = stmmac_default_data, }; +static int ehl_common_data(struct pci_dev *pdev, + struct plat_stmmacenet_data *plat) +{ + int i; + + plat->bus_id = 1; + plat->phy_addr = 0; + plat->clk_csr = 5; + plat->has_gmac = 0; + plat->has_gmac4 = 1; + plat->force_sf_dma_mode = 0; + plat->tso_en = 1; + + plat->rx_queues_to_use = 8; + plat->tx_queues_to_use = 8; + plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; + + for (i = 0; i < plat->rx_queues_to_use; i++) { + plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; + plat->rx_queues_cfg[i].chan = i; + + /* Disable Priority config by default */ + plat->tx_queues_cfg[i].use_prio = false; + + /* Disable RX queues routing by default */ + plat->rx_queues_cfg[i].pkt_route = 0x0; + } + + for (i = 0; i < plat->tx_queues_to_use; i++) { + plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; + + /* Disable Priority config by default */ + plat->tx_queues_cfg[i].use_prio = false; + } + + plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; + plat->tx_queues_cfg[0].weight = 0x09; + plat->tx_queues_cfg[1].weight = 0x0A; + plat->tx_queues_cfg[2].weight = 0x0B; + plat->tx_queues_cfg[3].weight = 0x0C; + plat->tx_queues_cfg[4].weight = 0x0D; + plat->tx_queues_cfg[5].weight = 0x0E; + plat->tx_queues_cfg[6].weight = 0x0F; + plat->tx_queues_cfg[7].weight = 0x10; + + plat->mdio_bus_data->phy_reset = NULL; + plat->mdio_bus_data->phy_mask = 0; + + plat->dma_cfg->pbl = 32; + plat->dma_cfg->pblx8 = true; + plat->dma_cfg->fixed_burst = 0; + plat->dma_cfg->mixed_burst = 0; + plat->dma_cfg->aal = 0; + + plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), + GFP_KERNEL); + if (!plat->axi) + return -ENOMEM; + plat->axi->axi_lpi_en = 0; + plat->axi->axi_xit_frm = 0; + plat->axi->axi_wr_osr_lmt = 0; + plat->axi->axi_rd_osr_lmt = 2; + plat->axi->axi_blen[0] = 4; + plat->axi->axi_blen[1] = 8; + plat->axi->axi_blen[2] = 16; + + /* Set default value for multicast hash bins */ + plat->multicast_filter_bins = HASH_TABLE_SIZE; + + /* Set default value for unicast filter entries */ + plat->unicast_filter_entries = 1; + + /* Set the maxmtu to a default of JUMBO_LEN */ + plat->maxmtu = JUMBO_LEN; + + plat->tx_fifo_size = 32768; + plat->rx_fifo_size = 32768; + + return 0; +} + +static int ehl_sgmii1g_data(struct pci_dev *pdev, + struct plat_stmmacenet_data *plat) +{ + int ret; + + /* Set common default data first */ + ret = ehl_common_data(pdev, plat); + + if (ret) + return ret; + + plat->interface = PHY_INTERFACE_MODE_SGMII; + + return 0; +} + +static struct stmmac_pci_info ehl_sgmii1g_pci_info = { + .setup = ehl_sgmii1g_data, +}; + static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { { .func = 6, @@ -355,6 +456,7 @@ static int __maybe_unused stmmac_pci_resume(struct device *dev) #define STMMAC_QUARK_ID 0x0937 #define STMMAC_DEVICE_ID 0x1108 +#define STMMAC_EHL_SGMII1G_ID 0x4b31 #define STMMAC_DEVICE(vendor_id, dev_id, info) { \ PCI_VDEVICE(vendor_id, dev_id), \ @@ -365,6 +467,7 @@ static int __maybe_unused stmmac_pci_resume(struct device *dev) STMMAC_DEVICE(STMMAC, STMMAC_DEVICE_ID, stmmac_pci_info), STMMAC_DEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_MAC, stmmac_pci_info), STMMAC_DEVICE(INTEL, STMMAC_QUARK_ID, quark_pci_info), + STMMAC_DEVICE(INTEL, STMMAC_EHL_SGMII1G_ID, ehl_sgmii1g_pci_info), {} };
Added EHL SGMII 1Gbps PCI ID. Different MII and speed will have different PCI ID. For EHL, default TX and RX FIFO size is set to 32KB. This is because the FIFO size advertised in the HW features is not the same as the HW implementation. The TX FIFO is shared among all all the TX queues and the RX FIFO is also shared among all the RX queues. Signed-off-by: Weifeng Voon <weifeng.voon@intel.com> --- drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 103 +++++++++++++++++++++++ 1 file changed, 103 insertions(+)