| Message ID | 1530134719-19407-2-git-send-email-steven.hill@cavium.com |
|---|---|
| State | Changes Requested, archived |
| Delegated to: | David Miller |
| Headers | show |
| Series | netdev: octeon-ethernet: Add Cavium Octeon III support. | expand |
> +- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay setting. > + Needed by the Micrel PHY. Could you explain this some more. Is it anything to do with RGMII delays? Thanks Andrew
On 06/28/2018 03:35 AM, Andrew Lunn wrote: > >> +- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay setting. >> + Needed by the Micrel PHY. > > Could you explain this some more. Is it anything to do with RGMII delays? > Andrew, One of my colleagues tracked this down for me. This device tree option is in place because there are several different ways to do the clock and data with respect to RGMII. This controls the delay introduced for the RX clock with respect to the data. Without this, RX will not work with Micrel PHYs. Thanks. Steve
On Fri, Jul 06, 2018 at 05:10:39PM -0500, Steven J. Hill wrote: > On 06/28/2018 03:35 AM, Andrew Lunn wrote: > > > >> +- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay setting. > >> + Needed by the Micrel PHY. > > > > Could you explain this some more. Is it anything to do with RGMII delays? > > > Andrew, > > One of my colleagues tracked this down for me. This device tree option is in place > because there are several different ways to do the clock and data with respect to > RGMII. This controls the delay introduced for the RX clock with respect to the data. > Without this, RX will not work with Micrel PHYs. Thanks. Hi Steven This is his RGMII delays, as i guess. Don't add this property, do it the Linux way. Look at phy-mode values phy.h: PHY_INTERFACE_MODE_RGMII_ID, phy.h: PHY_INTERFACE_MODE_RGMII_RXID, phy.h: PHY_INTERFACE_MODE_RGMII_TXID, There are plenty of examples in drivers/net/ethernet Andrew
diff --git a/Documentation/devicetree/bindings/net/cavium-bgx.txt b/Documentation/devicetree/bindings/net/cavium-bgx.txt new file mode 100644 index 0000000..21c9606 --- /dev/null +++ b/Documentation/devicetree/bindings/net/cavium-bgx.txt @@ -0,0 +1,59 @@ +* Common Ethernet Interface (BGX) block + +Properties: + +- compatible: "cavium,octeon-7890-bgx": Compatibility with all cn7xxx SOCs. + +- reg: The base address of the BGX block. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. BGX addresses have no size component. + +Typically a BGX block has several children each representing a ethernet +interface. + +Example: + + ethernet-mac-nexus@11800e0000000 { + compatible = "cavium,octeon-7890-bgx"; + reg = <0x00011800 0xe0000000 0x00000000 0x01000000>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-mac@0 { + ... + reg = <0>; + }; + }; + + +* Ethernet Interface (BGX port) connects to PKI/PKO + +Properties: + +- compatible: "cavium,octeon-7890-bgx-port": Compatibility with all cn7xxx + SOCs. + +- reg: The index of the interface withing the BGX block. + +- local-mac-address: Mac address for the interface. + +- phy-handle: phandle to the phy node connected to the interface. + + +* Ethernet Interface (BGX port) connects to XCV + + +Properties: + +- compatible: "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs. + +- reg: The index of the interface withing the BGX block. + +- local-mac-address: Mac address for the interface. + +- phy-handle: phandle to the phy node connected to the interface. + +- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay setting. + Needed by the Micrel PHY.