From patchwork Sat Jun 20 19:31:29 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lunn X-Patchwork-Id: 487027 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 28C2A1401AB for ; Sun, 21 Jun 2015 05:37:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932503AbbFTTh1 (ORCPT ); Sat, 20 Jun 2015 15:37:27 -0400 Received: from vps0.lunn.ch ([178.209.37.122]:60054 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932170AbbFTThZ (ORCPT ); Sat, 20 Jun 2015 15:37:25 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.80) (envelope-from ) id 1Z6OUH-00034u-DO; Sat, 20 Jun 2015 21:31:33 +0200 From: Andrew Lunn To: David Miller Cc: netdev , Guenter Roeck , Vivien Didelot , Cory Tusar , Andrew Lunn Subject: [PATCH] dsa: mv88x6xxx: Zero statistics counters Date: Sat, 20 Jun 2015 21:31:29 +0200 Message-Id: <1434828689-11804-1-git-send-email-andrew@lunn.ch> X-Mailer: git-send-email 1.7.10.4 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Zero the statistics counters when setting up the global registers. Otherwise the counters will remain from the last boot if the power has not been removed. Signed-off-by: Andrew Lunn --- This patch will only cleanly apply after the debug series. There is no actual dependency, so applying the patch with some fuzz will allow it to be applied without the debug series. drivers/net/dsa/mv88e6xxx.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/dsa/mv88e6xxx.c b/drivers/net/dsa/mv88e6xxx.c index cb6c2711d6ea..fc73d809c292 100644 --- a/drivers/net/dsa/mv88e6xxx.c +++ b/drivers/net/dsa/mv88e6xxx.c @@ -2061,6 +2061,12 @@ int mv88e6xxx_setup_global(struct dsa_switch *ds) 0x9000 | (i << 8)); } + /* Clear the statistics counters for all ports */ + REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL); + + /* Wait for the flush to complete. */ + _mv88e6xxx_stats_wait(ds); + return 0; }