powerpc/book3e: Fix extlb size

The calculation of the size for the exception save area of the TLB
miss handler is wrong, luckily it's too big not too small.

Rework it to make it a bit clearer, and also correct. We want 3 save
areas, each EX_TLB_SIZE _bytes_.

Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
 arch/powerpc/include/asm/paca.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

On Apr 5, 2011, at 1:28 AM, Michael Ellerman wrote:

> The calculation of the size for the exception save area of the TLB
> miss handler is wrong, luckily it's too big not too small.
> 
> Rework it to make it a bit clearer, and also correct. We want 3 save
> areas, each EX_TLB_SIZE _bytes_.

Where does the 3 come from?  I have a guess, and think its possible we (FSL) want 4?

> 
> Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
> ---
> arch/powerpc/include/asm/paca.h |    2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
> index ec57540..f7aa4fd 100644
> --- a/arch/powerpc/include/asm/paca.h
> +++ b/arch/powerpc/include/asm/paca.h
> @@ -106,7 +106,7 @@ struct paca_struct {
> 	pgd_t *pgd;			/* Current PGD */
> 	pgd_t *kernel_pgd;		/* Kernel PGD */
> 	u64 exgen[8] __attribute__((aligned(0x80)));
> -	u64 extlb[EX_TLB_SIZE*3] __attribute__((aligned(0x80)));
> +	u64 extlb[3][EX_TLB_SIZE / sizeof(u64)] __attribute__((aligned(0x80)));
> 	u64 exmc[8];		/* used for machine checks */
> 	u64 excrit[8];		/* used for crit interrupts */
> 	u64 exdbg[8];		/* used for debug interrupts */
> -- 
> 1.7.1
> 
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On Tue, 2011-04-05 at 07:41 -0500, Kumar Gala wrote:
> > Rework it to make it a bit clearer, and also correct. We want 3 save
> > areas, each EX_TLB_SIZE _bytes_.
> 
> Where does the 3 come from?  I have a guess, and think its possible we
> (FSL) want 4?

Wrong guess :-) It's not about exception levels. It's about how much
the handler can re-enter (2 with E.PT, 3 with virtual linear)

For MC's, CRITs etc... which we don't support on Book3E 64-bit at this
stage, you'll have to probably backup the whole area... that or move
the TLB frame pointer SPR to a separate set of 3 levels, but then you'd
have to fix the code that makes assumption about level 0 being at a
fixed offset in the PACA and instead use alignment tricks. We need that
because that's how we "reset" the TLB frame when a second level finds
a fault.

Cheers,
Ben.

On Apr 5, 2011, at 6:39 PM, Benjamin Herrenschmidt wrote:

> On Tue, 2011-04-05 at 07:41 -0500, Kumar Gala wrote:
>>> Rework it to make it a bit clearer, and also correct. We want 3 save
>>> areas, each EX_TLB_SIZE _bytes_.
>> 
>> Where does the 3 come from?  I have a guess, and think its possible we
>> (FSL) want 4?
> 
> Wrong guess :-) It's not about exception levels. It's about how much
> the handler can re-enter (2 with E.PT, 3 with virtual linear)
> 
> For MC's, CRITs etc... which we don't support on Book3E 64-bit at this
> stage, you'll have to probably backup the whole area... that or move
> the TLB frame pointer SPR to a separate set of 3 levels, but then you'd
> have to fix the code that makes assumption about level 0 being at a
> fixed offset in the PACA and instead use alignment tricks. We need that
> because that's how we "reset" the TLB frame when a second level finds
> a fault.
> 
> Cheers,
> Ben.

Gotcha, can we add a comment here about what the '3' is about.

- k