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[1/7] arch/powerpc/perf : Removing unused macros from power5+-pmu.c

Message ID 20250426035535.450778-2-likhitha@linux.ibm.com (mailing list archive)
State New
Headers show
Series Removing unused macros in arch/powerpc/perf | expand

Commit Message

Likhitha Korrapati April 26, 2025, 3:55 a.m. UTC 
The following macros were introduced in power5+-pmu via
commit aabbaa6036fd ("perfcounters/powerpc: add support
for POWER5+ processors")

MMCR1_TTM2SEL_SH, MMCR1_TTMSEL_MSK, MMCR1_TD_CP_DBG1SEL_SH,
MMCR1_TD_CP_DBG2SEL_SH, MMCR1_TD_CP_DBG3SEL_SH, MMCR1_GRS_L2SEL_MSK,
MMCR1_GRS_L3SEL_MSK, MMCR1_GRS_MCSEL_MSK, MMCR1_GRS_FABSEL_MSK
MMCR1_PMC2_ADDER_SEL_SH, MMCR1_PMC3_ADDER_SEL_SH, MMCR1_PMC4_ADDER_SEL_SH
MMCR1_PMC2SEL_SH, MMCR1_PMC3SEL_SH, MMCR1_PMC4SEL_SH, MMCR1_PMCSEL_MSK

Removing the above macros as they are defined but never used.

Co-developed-by: Anjali K <anjalik@linux.ibm.com>
Signed-off-by: Anjali K <anjalik@linux.ibm.com>
Signed-off-by: Likhitha Korrapati <likhitha@linux.ibm.com>
---
 arch/powerpc/perf/power5+-pmu.c | 16 ----------------
 1 file changed, 16 deletions(-)
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Patch

diff --git a/arch/powerpc/perf/power5+-pmu.c b/arch/powerpc/perf/power5+-pmu.c
index b4708ab73145..8ece241f8e48 100644
--- a/arch/powerpc/perf/power5+-pmu.c
+++ b/arch/powerpc/perf/power5+-pmu.c
@@ -44,31 +44,15 @@ 
  */
 #define MMCR1_TTM0SEL_SH	62
 #define MMCR1_TTM1SEL_SH	60
-#define MMCR1_TTM2SEL_SH	58
 #define MMCR1_TTM3SEL_SH	56
-#define MMCR1_TTMSEL_MSK	3
 #define MMCR1_TD_CP_DBG0SEL_SH	54
-#define MMCR1_TD_CP_DBG1SEL_SH	52
-#define MMCR1_TD_CP_DBG2SEL_SH	50
-#define MMCR1_TD_CP_DBG3SEL_SH	48
 #define MMCR1_GRS_L2SEL_SH	46
-#define MMCR1_GRS_L2SEL_MSK	3
 #define MMCR1_GRS_L3SEL_SH	44
-#define MMCR1_GRS_L3SEL_MSK	3
 #define MMCR1_GRS_MCSEL_SH	41
-#define MMCR1_GRS_MCSEL_MSK	7
 #define MMCR1_GRS_FABSEL_SH	39
-#define MMCR1_GRS_FABSEL_MSK	3
 #define MMCR1_PMC1_ADDER_SEL_SH	35
-#define MMCR1_PMC2_ADDER_SEL_SH	34
-#define MMCR1_PMC3_ADDER_SEL_SH	33
-#define MMCR1_PMC4_ADDER_SEL_SH	32
 #define MMCR1_PMC1SEL_SH	25
-#define MMCR1_PMC2SEL_SH	17
-#define MMCR1_PMC3SEL_SH	9
-#define MMCR1_PMC4SEL_SH	1
 #define MMCR1_PMCSEL_SH(n)	(MMCR1_PMC1SEL_SH - (n) * 8)
-#define MMCR1_PMCSEL_MSK	0x7f
 
 /*
  * Layout of constraint bits: