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Wed, 22 Mar 2023 05:46:35 +0000 (GMT) Received: from bgray-lenovo-p15.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 8544A60511; Wed, 22 Mar 2023 16:46:32 +1100 (AEDT) From: Benjamin Gray To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 3/9] powerpc/dexcr: Handle hashchk exception Date: Wed, 22 Mar 2023 16:46:06 +1100 Message-Id: <20230322054612.1340573-4-bgray@linux.ibm.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230322054612.1340573-1-bgray@linux.ibm.com> References: <20230322054612.1340573-1-bgray@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: uHmCyl49lCz8SRN1x1GR8wyvOJQNHmwB X-Proofpoint-GUID: uHmCyl49lCz8SRN1x1GR8wyvOJQNHmwB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-21_11,2023-03-21_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 mlxlogscore=611 spamscore=0 phishscore=0 malwarescore=0 suspectscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303150002 definitions=main-2303220039 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Benjamin Gray Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Recognise and pass the appropriate signal to the user program when a hashchk instruction triggers. This is independent of allowing configuration of DEXCR[NPHIE], as a hypervisor can enforce this aspect regardless of the kernel. The signal mirrors how ARM reports their similar check failure. For example, their FPAC handler in arch/arm64/kernel/traps.c do_el0_fpac() does this. When we fail to read the instruction that caused the fault we send a segfault, similar to how emulate_math() does it. Signed-off-by: Benjamin Gray --- v1: * Refactor the hashchk check to return 0 on success, an error code on failure. Determine what to do based on specific error code. * Motivate signal and code --- arch/powerpc/include/asm/ppc-opcode.h | 1 + arch/powerpc/include/asm/processor.h | 9 +++++++ arch/powerpc/kernel/Makefile | 1 + arch/powerpc/kernel/dexcr.c | 36 +++++++++++++++++++++++++++ arch/powerpc/kernel/traps.c | 10 ++++++++ 5 files changed, 57 insertions(+) create mode 100644 arch/powerpc/kernel/dexcr.c diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 21e33e46f4b8..89b316466ed1 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -215,6 +215,7 @@ #define OP_31_XOP_STFSX 663 #define OP_31_XOP_STFSUX 695 #define OP_31_XOP_STFDX 727 +#define OP_31_XOP_HASHCHK 754 #define OP_31_XOP_STFDUX 759 #define OP_31_XOP_LHBRX 790 #define OP_31_XOP_LFIWAX 855 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index e96c9b8c2a60..bad64d6a5d36 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -455,6 +455,15 @@ int exit_vmx_usercopy(void); int enter_vmx_ops(void); void *exit_vmx_ops(void *dest); +#ifdef CONFIG_PPC_BOOK3S_64 +int check_hashchk_trap(struct pt_regs const *regs); +#else +static inline int check_hashchk_trap(struct pt_regs const *regs) +{ + return -EINVAL; +} +#endif /* CONFIG_PPC_BOOK3S_64 */ + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ #endif /* _ASM_POWERPC_PROCESSOR_H */ diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index 9bf2be123093..07181e508754 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile @@ -88,6 +88,7 @@ obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o obj-$(CONFIG_PPC_DAWR) += dawr.o obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o cpu_setup_pa6t.o obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power.o +obj-$(CONFIG_PPC_BOOK3S_64) += dexcr.o obj-$(CONFIG_PPC_BOOK3S_64) += mce.o mce_power.o obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_64e.o obj-$(CONFIG_PPC_BARRIER_NOSPEC) += security.o diff --git a/arch/powerpc/kernel/dexcr.c b/arch/powerpc/kernel/dexcr.c new file mode 100644 index 000000000000..f263e5439cc6 --- /dev/null +++ b/arch/powerpc/kernel/dexcr.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * DEXCR infrastructure + * + * Copyright 2023, Benjamin Gray, IBM Corporation. + */ +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +int check_hashchk_trap(struct pt_regs const *regs) +{ + ppc_inst_t insn; + + if (!cpu_has_feature(CPU_FTR_DEXCR_NPHIE)) + return -EINVAL; + + if (!user_mode(regs)) + return -EINVAL; + + if (get_user_instr(insn, (void __user *)regs->nip)) + return -EFAULT; + + if (ppc_inst_primary_opcode(insn) != 31 || + get_xop(ppc_inst_val(insn)) != OP_31_XOP_HASHCHK) + return -EINVAL; + + return 0; +} diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index 9bdd79aa51cf..ade67e23b974 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -1516,6 +1516,16 @@ static void do_program_check(struct pt_regs *regs) return; } } + + switch (check_hashchk_trap(regs)) { + case 0: + _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); + return; + case -EFAULT: + _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); + return; + } + _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); return; }