Message ID | 20230320070339.915172-11-npiggin@gmail.com (mailing list archive) |
---|---|
State | Handled Elsewhere |
Headers | show |
Series | powerpc: updates, P10, PNV support | expand |
On 20/03/2023 08.03, Nicholas Piggin wrote: > This enables HV privilege registers to be tested with the powernv > machine. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > --- > powerpc/sprs.c | 31 ++++++++++++++++++++++++------- > 1 file changed, 24 insertions(+), 7 deletions(-) > > diff --git a/powerpc/sprs.c b/powerpc/sprs.c > index dd83dac..a7878ff 100644 > --- a/powerpc/sprs.c > +++ b/powerpc/sprs.c > @@ -199,16 +199,16 @@ static const struct spr sprs_power_common[1024] = { > [190] = {"HFSCR", 64, HV_RW, }, > [256] = {"VRSAVE", 32, RW, }, > [259] = {"SPRG3", 64, RO, }, > -[284] = {"TBL", 32, HV_WO, }, > -[285] = {"TBU", 32, HV_WO, }, > -[286] = {"TBU40", 64, HV_WO, }, > +[284] = {"TBL", 32, HV_WO, }, /* Things can go a bit wonky with */ > +[285] = {"TBU", 32, HV_WO, }, /* Timebase changing. Should save */ > +[286] = {"TBU40", 64, HV_WO, }, /* and restore it. */ > [304] = {"HSPRG0", 64, HV_RW, }, > [305] = {"HSPRG1", 64, HV_RW, }, > [306] = {"HDSISR", 32, HV_RW, SPR_INT, }, > [307] = {"HDAR", 64, HV_RW, SPR_INT, }, > [308] = {"SPURR", 64, HV_RW | OS_RO, SPR_ASYNC, }, > [309] = {"PURR", 64, HV_RW | OS_RO, SPR_ASYNC, }, > -[313] = {"HRMOR", 64, HV_RW, }, > +[313] = {"HRMOR", 64, HV_RW, SPR_HARNESS, }, /* Harness can't cope with HRMOR changing */ > [314] = {"HSRR0", 64, HV_RW, SPR_INT, }, > [315] = {"HSRR1", 64, HV_RW, SPR_INT, }, > [318] = {"LPCR", 64, HV_RW, }, > @@ -350,6 +350,22 @@ static const struct spr sprs_power10_pmu[1024] = { > > static struct spr sprs[1024]; > > +static bool spr_read_perms(int spr) > +{ > + if (machine_is_powernv()) > + return !!(sprs[spr].access & SPR_HV_READ); > + else > + return !!(sprs[spr].access & SPR_OS_READ); > +} > + > +static bool spr_write_perms(int spr) > +{ > + if (machine_is_powernv()) > + return !!(sprs[spr].access & SPR_HV_WRITE); > + else > + return !!(sprs[spr].access & SPR_OS_WRITE); > +} > + > static void setup_sprs(void) > { > uint32_t pvr = mfspr(287); /* Processor Version Register */ > @@ -462,7 +478,7 @@ static void get_sprs(uint64_t *v) > int i; > > for (i = 0; i < 1024; i++) { > - if (!(sprs[i].access & SPR_OS_READ)) > + if (!spr_read_perms(i)) > continue; > v[i] = mfspr(i); > } > @@ -473,8 +489,9 @@ static void set_sprs(uint64_t val) > int i; > > for (i = 0; i < 1024; i++) { > - if (!(sprs[i].access & SPR_OS_WRITE)) > + if (!spr_write_perms(i)) > continue; > + > if (sprs[i].type & SPR_HARNESS) > continue; > if (!strcmp(sprs[i].name, "MMCR0")) { > @@ -546,7 +563,7 @@ int main(int argc, char **argv) > for (i = 0; i < 1024; i++) { > bool pass = true; > > - if (!(sprs[i].access & SPR_OS_READ)) > + if (!spr_read_perms(i)) > continue; > > if (sprs[i].width == 32) { Acked-by: Thomas Huth <thuth@redhat.com>
diff --git a/powerpc/sprs.c b/powerpc/sprs.c index dd83dac..a7878ff 100644 --- a/powerpc/sprs.c +++ b/powerpc/sprs.c @@ -199,16 +199,16 @@ static const struct spr sprs_power_common[1024] = { [190] = {"HFSCR", 64, HV_RW, }, [256] = {"VRSAVE", 32, RW, }, [259] = {"SPRG3", 64, RO, }, -[284] = {"TBL", 32, HV_WO, }, -[285] = {"TBU", 32, HV_WO, }, -[286] = {"TBU40", 64, HV_WO, }, +[284] = {"TBL", 32, HV_WO, }, /* Things can go a bit wonky with */ +[285] = {"TBU", 32, HV_WO, }, /* Timebase changing. Should save */ +[286] = {"TBU40", 64, HV_WO, }, /* and restore it. */ [304] = {"HSPRG0", 64, HV_RW, }, [305] = {"HSPRG1", 64, HV_RW, }, [306] = {"HDSISR", 32, HV_RW, SPR_INT, }, [307] = {"HDAR", 64, HV_RW, SPR_INT, }, [308] = {"SPURR", 64, HV_RW | OS_RO, SPR_ASYNC, }, [309] = {"PURR", 64, HV_RW | OS_RO, SPR_ASYNC, }, -[313] = {"HRMOR", 64, HV_RW, }, +[313] = {"HRMOR", 64, HV_RW, SPR_HARNESS, }, /* Harness can't cope with HRMOR changing */ [314] = {"HSRR0", 64, HV_RW, SPR_INT, }, [315] = {"HSRR1", 64, HV_RW, SPR_INT, }, [318] = {"LPCR", 64, HV_RW, }, @@ -350,6 +350,22 @@ static const struct spr sprs_power10_pmu[1024] = { static struct spr sprs[1024]; +static bool spr_read_perms(int spr) +{ + if (machine_is_powernv()) + return !!(sprs[spr].access & SPR_HV_READ); + else + return !!(sprs[spr].access & SPR_OS_READ); +} + +static bool spr_write_perms(int spr) +{ + if (machine_is_powernv()) + return !!(sprs[spr].access & SPR_HV_WRITE); + else + return !!(sprs[spr].access & SPR_OS_WRITE); +} + static void setup_sprs(void) { uint32_t pvr = mfspr(287); /* Processor Version Register */ @@ -462,7 +478,7 @@ static void get_sprs(uint64_t *v) int i; for (i = 0; i < 1024; i++) { - if (!(sprs[i].access & SPR_OS_READ)) + if (!spr_read_perms(i)) continue; v[i] = mfspr(i); } @@ -473,8 +489,9 @@ static void set_sprs(uint64_t val) int i; for (i = 0; i < 1024; i++) { - if (!(sprs[i].access & SPR_OS_WRITE)) + if (!spr_write_perms(i)) continue; + if (sprs[i].type & SPR_HARNESS) continue; if (!strcmp(sprs[i].name, "MMCR0")) { @@ -546,7 +563,7 @@ int main(int argc, char **argv) for (i = 0; i < 1024; i++) { bool pass = true; - if (!(sprs[i].access & SPR_OS_READ)) + if (!spr_read_perms(i)) continue; if (sprs[i].width == 32) {
This enables HV privilege registers to be tested with the powernv machine. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- powerpc/sprs.c | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-)