| Message ID | 20220725063156.121292-1-rmclure@linux.ibm.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | powerpc: Syscall wrapper and register clearing | expand |
On Mon, 2022-07-25 at 16:31 +1000, Rohan McLure wrote: > Interrupt handlers on 64s systems will often need to save register > state > from the interrupted process to make space for loading special > purpose > registers or for internal state. > > Fix a comment documenting a common code path macro in the beginning > of > interrupt handlers where r10 is saved to the PACA to afford space for > the value of the CFAR. Comment is currently written as if r10-r12 are > saved to PACA, but in fact only r10 is saved. > > Signed-off-by: Rohan McLure <rmclure@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Le 25/07/2022 à 08:31, Rohan McLure a écrit : > Interrupt handlers on 64s systems will often need to save register state > from the interrupted process to make space for loading special purpose > registers or for internal state. > > Fix a comment documenting a common code path macro in the beginning of > interrupt handlers where r10 is saved to the PACA to afford space for > the value of the CFAR. Comment is currently written as if r10-r12 are > saved to PACA, but in fact only r10 is saved. Maybe it would be interesting to know from which patch the error comes. > > Signed-off-by: Rohan McLure <rmclure@linux.ibm.com> > --- > V1 -> V2: Given its own commit > --- > arch/powerpc/kernel/exceptions-64s.S | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S > index b66dd6f775a4..102896fc6a86 100644 > --- a/arch/powerpc/kernel/exceptions-64s.S > +++ b/arch/powerpc/kernel/exceptions-64s.S > @@ -281,7 +281,7 @@ BEGIN_FTR_SECTION > mfspr r9,SPRN_PPR > END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) > HMT_MEDIUM > - std r10,IAREA+EX_R10(r13) /* save r10 - r12 */ > + std r10,IAREA+EX_R10(r13) /* save r10 */ > .if ICFAR > BEGIN_FTR_SECTION > mfspr r10,SPRN_CFAR
> Maybe it would be interesting to know from which patch the error comes.
It’s hard to attribute this to a single commit, but the distance between r10’s save
location and r11-r12’s save location has definitely grown over time. The comment is
introduced in commit 7180e3e636de
("[POWERPC] force 64bit mode in fwnmi handlers to workaround firmware bugs”) way back in 2006.
In v3 will insert another comment to better signal where r11-r12 are saved.
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index b66dd6f775a4..102896fc6a86 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -281,7 +281,7 @@ BEGIN_FTR_SECTION mfspr r9,SPRN_PPR END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) HMT_MEDIUM - std r10,IAREA+EX_R10(r13) /* save r10 - r12 */ + std r10,IAREA+EX_R10(r13) /* save r10 */ .if ICFAR BEGIN_FTR_SECTION mfspr r10,SPRN_CFAR
Interrupt handlers on 64s systems will often need to save register state from the interrupted process to make space for loading special purpose registers or for internal state. Fix a comment documenting a common code path macro in the beginning of interrupt handlers where r10 is saved to the PACA to afford space for the value of the CFAR. Comment is currently written as if r10-r12 are saved to PACA, but in fact only r10 is saved. Signed-off-by: Rohan McLure <rmclure@linux.ibm.com> --- V1 -> V2: Given its own commit --- arch/powerpc/kernel/exceptions-64s.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)