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Thu, 27 Jan 2022 07:21:40 +0000 (GMT) From: Kajol Jain To: mpe@ellerman.id.au Subject: [PATCH 20/20] selftest/powerpc/pmu: Add interface test for mmcra register fields Date: Thu, 27 Jan 2022 12:50:12 +0530 Message-Id: <20220127072012.662451-21-kjain@linux.ibm.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220127072012.662451-1-kjain@linux.ibm.com> References: <20220127072012.662451-1-kjain@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: e6InFPaoNr_IB5WvdWWPvwmf3ckaYZlH X-Proofpoint-ORIG-GUID: e6InFPaoNr_IB5WvdWWPvwmf3ckaYZlH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-27_01,2022-01-26_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 spamscore=0 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 mlxscore=0 mlxlogscore=999 clxscore=1015 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201270036 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kjain@linux.ibm.com, atrajeev@linux.vnet.ibm.com, maddy@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org, rnsastry@linux.ibm.com Errors-To: linuxppc-dev-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The testcase uses event code 0x35340401e0 to verify the settings for different fields in Monitor Mode Control Register A (MMCRA). The fields include thresh_start, thresh_stop thresh_select, sdar mode, sample and marked bit. Checks if these fields are translated correctly via perf interface to MMCRA. Signed-off-by: Kajol Jain --- .../powerpc/pmu/sampling_tests/Makefile | 4 +- .../mmcra_thresh_marked_sample_test.c | 80 +++++++++++++++++++ 2 files changed, 82 insertions(+), 2 deletions(-) create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_thresh_marked_sample_test.c diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile index 58d3ddf779d2..a9bf343df911 100644 --- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile +++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile @@ -4,7 +4,7 @@ include ../../../../../../scripts/Kbuild.include all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c mmcr0_cc56run_test.c mmcr0_pmccext_test.c \ mmcr0_pmcjce_test.c mmcr0_fc56_pmc1ce_test.c mmcr0_fc56_pmc56_test.c \ mmcr1_comb_test.c mmcr1_sel_unit_cache_test.c mmcr2_l2l3_test.c \ - mmcr2_fcs_fch_test.c mmcr3_src_test.c + mmcr2_fcs_fch_test.c mmcr3_src_test.c mmcra_thresh_marked_sample_test.c noarg: $(MAKE) -C ../../ @@ -18,7 +18,7 @@ no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \ TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test mmcr0_pmccext_test \ mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test mmcr0_fc56_pmc56_test \ mmcr1_comb_test mmcr1_sel_unit_cache_test mmcr2_l2l3_test \ - mmcr2_fcs_fch_test mmcr3_src_test + mmcr2_fcs_fch_test mmcr3_src_test mmcra_thresh_marked_sample_test LDFLAGS += $(no-pie-option) diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_thresh_marked_sample_test.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_thresh_marked_sample_test.c new file mode 100644 index 000000000000..ca6bdb335fa5 --- /dev/null +++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_thresh_marked_sample_test.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2022, Kajol Jain, IBM Corp. + */ + +#include +#include + +#include "../event.h" +#include "misc.h" +#include "utils.h" + +/* + * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0) + * Threshold event selection used is issue to complete for cycles + * Sampling criteria is Load only sampling + */ +#define EventCode 0x35340401e0 + +extern void thirty_two_instruction_loop_with_ll_sc(u64 loops, u64 *ll_sc_target); + +/* A perf sampling test to test mmcra fields */ +static int mmcra_thresh_marked_sample(void) +{ + struct event event; + u64 *intr_regs; + u64 dummy; + + /* Check for platform support for the test */ + SKIP_IF(check_pvr_for_sampling_tests()); + + /* Init the event for the sampling test */ + event_init_sampling(&event, EventCode); + event.attr.sample_regs_intr = platform_extended_mask; + FAIL_IF(event_open(&event)); + event.mmap_buffer = event_sample_buf_mmap(event.fd, 1); + + event_enable(&event); + + /* workload to make the event overflow */ + thirty_two_instruction_loop_with_ll_sc(1000000, &dummy); + + event_disable(&event); + + /* Check for sample count */ + FAIL_IF(!collect_samples(event.mmap_buffer)); + + intr_regs = get_intr_regs(&event, event.mmap_buffer); + + /* Check for intr_regs */ + FAIL_IF(!intr_regs); + + /* + * Verify that thresh sel/start/stop, marked, random sample + * eligibility, sdar mode and sample mode fields match with + * the corresponding event code fields + */ + FAIL_IF(EV_CODE_EXTRACT(event.attr.config, thd_sel) != + GET_MMCR_FIELD(A, get_reg_value(intr_regs, "MMCRA"), 4, thd_sel)); + FAIL_IF(EV_CODE_EXTRACT(event.attr.config, thd_start) != + GET_MMCR_FIELD(A, get_reg_value(intr_regs, "MMCRA"), 4, thd_start)); + FAIL_IF(EV_CODE_EXTRACT(event.attr.config, thd_stop) != + GET_MMCR_FIELD(A, get_reg_value(intr_regs, "MMCRA"), 4, thd_stop)); + FAIL_IF(EV_CODE_EXTRACT(event.attr.config, marked) != + GET_MMCR_FIELD(A, get_reg_value(intr_regs, "MMCRA"), 4, marked)); + FAIL_IF(EV_CODE_EXTRACT(event.attr.config, sample >> 2) != + GET_MMCR_FIELD(A, get_reg_value(intr_regs, "MMCRA"), 4, rand_samp_elig)); + FAIL_IF(EV_CODE_EXTRACT(event.attr.config, sample & 0x3) != + GET_MMCR_FIELD(A, get_reg_value(intr_regs, "MMCRA"), 4, sample_mode)); + FAIL_IF(EV_CODE_EXTRACT(event.attr.config, sm) != + GET_MMCR_FIELD(A, get_reg_value(intr_regs, "MMCRA"), 4, sm)); + + event_close(&event); + return 0; +} + +int main(void) +{ + FAIL_IF(test_harness(mmcra_thresh_marked_sample, "mmcra_thresh_marked_sample")); +}