[16/20] selftest/powerpc/pmu/: Add selftest for mmcr1 pmcxsel/unit/cache fields

From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>

The testcase uses event code "0x1340000001c040" to verify
the settings for different fields in Monitor Mode Control
Register 1 (MMCR1). The fields include PMCxSEL, PMCXCOMB
PMCxUNIT, cache. Checks if these fields are translated
correctly via perf interface to MMCR1

Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
---
 .../powerpc/pmu/sampling_tests/Makefile       |  4 +-
 .../mmcr1_sel_unit_cache_test.c               | 70 +++++++++++++++++++
 2 files changed, 72 insertions(+), 2 deletions(-)
 create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_sel_unit_cache_test.c

Le 27/01/2022 à 08:20, Kajol Jain a écrit :
> From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
> 
> The testcase uses event code "0x1340000001c040" to verify
> the settings for different fields in Monitor Mode Control
> Register 1 (MMCR1). The fields include PMCxSEL, PMCXCOMB
> PMCxUNIT, cache. Checks if these fields are translated
> correctly via perf interface to MMCR1
> 
> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>

I see the series has been accepted but this patch has been left over.

Any reason ?

Thanks
Christophe


> ---
>   .../powerpc/pmu/sampling_tests/Makefile       |  4 +-
>   .../mmcr1_sel_unit_cache_test.c               | 70 +++++++++++++++++++
>   2 files changed, 72 insertions(+), 2 deletions(-)
>   create mode 100644 tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_sel_unit_cache_test.c
> 
> diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
> index bb5ffd2e322d..345ad66bd1b2 100644
> --- a/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
> +++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
> @@ -3,7 +3,7 @@ include ../../../../../../scripts/Kbuild.include
>   
>   all: $(TEST_GEN_PROGS) mmcr0_exceptionbits_test.c mmcr0_cc56run_test.c mmcr0_pmccext_test.c \
>   			mmcr0_pmcjce_test.c mmcr0_fc56_pmc1ce_test.c mmcr0_fc56_pmc56_test.c \
> -			mmcr1_comb_test.c
> +			mmcr1_comb_test.c mmcr1_sel_unit_cache_test.c
>   
>   noarg:
>   	$(MAKE) -C ../../
> @@ -16,7 +16,7 @@ no-pie-option := $(call try-run, echo 'int main() { return 0; }' | \
>   
>   TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test mmcr0_pmccext_test \
>   		   mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test mmcr0_fc56_pmc56_test \
> -		   mmcr1_comb_test
> +		   mmcr1_comb_test mmcr1_sel_unit_cache_test
>   
>   LDFLAGS += $(no-pie-option)
>   
> diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_sel_unit_cache_test.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_sel_unit_cache_test.c
> new file mode 100644
> index 000000000000..1a4d19c11017
> --- /dev/null
> +++ b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_sel_unit_cache_test.c
> @@ -0,0 +1,70 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright 2022, Athira Rajeev, IBM Corp.
> + */
> +
> +#include <stdio.h>
> +#include <stdlib.h>
> +
> +#include "../event.h"
> +#include "misc.h"
> +#include "utils.h"
> +
> +extern void thirty_two_instruction_loop_with_ll_sc(u64 loops, u64 *ll_sc_target);
> +
> +/* The data cache was reloaded from local core's L3 due to a demand load */
> +#define EventCode 0x21c040
> +
> +/*
> + * A perf sampling test for mmcr1
> + * fields : pmcxsel, unit, cache.
> + */
> +static int mmcr1_sel_unit_cache(void)
> +{
> +	struct event event;
> +	u64 *intr_regs;
> +	u64 dummy;
> +
> +	/* Check for platform support for the test */
> +	SKIP_IF(check_pvr_for_sampling_tests());
> +
> +	/* Init the event for the sampling test */
> +	event_init_sampling(&event, EventCode);
> +	event.attr.sample_regs_intr = platform_extended_mask;
> +	FAIL_IF(event_open(&event));
> +	event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
> +
> +	event_enable(&event);
> +
> +	/* workload to make the event overflow */
> +	thirty_two_instruction_loop_with_ll_sc(10000000, &dummy);
> +
> +	event_disable(&event);
> +
> +	/* Check for sample count */
> +	FAIL_IF(!collect_samples(event.mmap_buffer));
> +
> +	intr_regs = get_intr_regs(&event, event.mmap_buffer);
> +
> +	/* Check for intr_regs */
> +	FAIL_IF(!intr_regs);
> +
> +	/*
> +	 * Verify that  pmcxsel, unit and cache field of MMCR1
> +	 * match with corresponding event code fields
> +	 */
> +	FAIL_IF(EV_CODE_EXTRACT(event.attr.config, pmcxsel) !=
> +			GET_MMCR_FIELD(1, get_reg_value(intr_regs, "MMCR1"), 1, pmcxsel));
> +	FAIL_IF(EV_CODE_EXTRACT(event.attr.config, unit) !=
> +			GET_MMCR_FIELD(1, get_reg_value(intr_regs, "MMCR1"), 1, unit));
> +	FAIL_IF(EV_CODE_EXTRACT(event.attr.config, cache) !=
> +			GET_MMCR_FIELD(1, get_reg_value(intr_regs, "MMCR1"), 1, cache));
> +
> +	event_close(&event);
> +	return 0;
> +}
> +
> +int main(void)
> +{
> +	FAIL_IF(test_harness(mmcr1_sel_unit_cache, "mmcr1_sel_unit_cache"));
> +}

Christophe Leroy <christophe.leroy@csgroup.eu> writes:
> Le 27/01/2022 à 08:20, Kajol Jain a écrit :
>> From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
>> 
>> The testcase uses event code "0x1340000001c040" to verify
>> the settings for different fields in Monitor Mode Control
>> Register 1 (MMCR1). The fields include PMCxSEL, PMCXCOMB
>> PMCxUNIT, cache. Checks if these fields are translated
>> correctly via perf interface to MMCR1
>> 
>> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
>
> I see the series has been accepted but this patch has been left over.
>
> Any reason ?

Yeah it's flakey. It counts cache loads but the workload it runs doesn't
necessarily cause any, so it sometimes fails. I've reported that
privately to Kajol.

cheers

On 3/10/22 17:41, Michael Ellerman wrote:
> Christophe Leroy <christophe.leroy@csgroup.eu> writes:
>> Le 27/01/2022 à 08:20, Kajol Jain a écrit :
>>> From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
>>>
>>> The testcase uses event code "0x1340000001c040" to verify
>>> the settings for different fields in Monitor Mode Control
>>> Register 1 (MMCR1). The fields include PMCxSEL, PMCXCOMB
>>> PMCxUNIT, cache. Checks if these fields are translated
>>> correctly via perf interface to MMCR1
>>>
>>> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
>>
>> I see the series has been accepted but this patch has been left over.
>>
>> Any reason ?
> 
> Yeah it's flakey. It counts cache loads but the workload it runs doesn't
> necessarily cause any, so it sometimes fails. I've reported that
> privately to Kajol.
> 

Hi Christophe,
     As Michael mentioned, with the current workload we used in this
patch, the testcase was failing sometimes as required cache load not
happening everytime. We will send this patch separately with proper
workload in next version.

Thanks,
Kajol Jain

> cheers