diff mbox series

[3/3] powerpc/perf: Fix data source encodings for power10

Message ID 20210904064932.307610-3-kjain@linux.ibm.com (mailing list archive)
State Changes Requested
Headers show
Series [1/3] perf: Add macros to specify onchip L2/L3 accesses | expand

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Commit Message

Kajol Jain Sept. 4, 2021, 6:49 a.m. UTC 
Fix the data source encodings for power10 to represent
onchip L2/L3 accesses properly.

Fixes: 79e96f8f930d ("powerpc/perf: Export memory hierarchy info to user
space")
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
---
 arch/powerpc/perf/isa207-common.c | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)
diff mbox series

Patch

diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c
index f92bf5f6b74f..9630a17c5da4 100644
--- a/arch/powerpc/perf/isa207-common.c
+++ b/arch/powerpc/perf/isa207-common.c
@@ -238,11 +238,22 @@  static inline u64 isa207_find_source(u64 idx, u32 sub_idx)
 		ret |= P(SNOOP, HIT);
 		break;
 	case 5:
-		ret = PH(LVL, REM_CCE1);
-		if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4))
-			ret |= P(SNOOP, HIT);
-		else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5))
-			ret |= P(SNOOP, HITM);
+		if (cpu_has_feature(CPU_FTR_ARCH_31)) {
+			if (sub_idx == 0 || sub_idx == 4)
+				ret = PH(LVLNUM, OC_L2) | P(SNOOP, HIT);
+			else if (sub_idx == 1 || sub_idx == 5)
+				ret = PH(LVLNUM, OC_L2) | P(SNOOP, HITM);
+			else if (sub_idx == 2 || sub_idx == 6)
+				ret = PH(LVLNUM, OC_L3) | P(SNOOP, HIT);
+			else if (sub_idx == 3 || sub_idx == 7)
+				ret = PH(LVLNUM, OC_L3) | P(SNOOP, HITM);
+		} else {
+			ret = PH(LVL, REM_CCE1);
+			if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4))
+				ret |= P(SNOOP, HIT);
+			else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5))
+				ret |= P(SNOOP, HITM);
+		}
 		break;
 	case 6:
 		ret = PH(LVL, REM_CCE2);