| Message ID | 20201012103128.53243-1-maddy@linux.ibm.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | powerpc/perf: fix Threshold Event CounterMultiplier width for P10 | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch powerpc/merge (118be7377c97e35c33819bcb3bbbae5a42a4ac43) |
| snowpatch_ozlabs/build-ppc64le | warning | Upstream build failed, couldn't test patch |
| snowpatch_ozlabs/build-ppc64be | warning | Upstream build failed, couldn't test patch |
| snowpatch_ozlabs/build-ppc64e | warning | Upstream build failed, couldn't test patch |
| snowpatch_ozlabs/build-pmac32 | warning | Upstream build failed, couldn't test patch |
| snowpatch_ozlabs/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 19 lines checked |
| snowpatch_ozlabs/needsstable | warning | Please consider tagging this patch for stable! |
Hello, On Mon, Oct 12, 2020 at 04:01:28PM +0530, Madhavan Srinivasan wrote: > Power9 and isa v3.1 has 7bit mantissa field for Threshold Event Counter ^^^ Shouldn't his be 3.0? > Multiplier (TECM). TECM is part of Monitor Mode Control Register A (MMCRA). > This field along with Threshold Event Counter Exponent (TECE) is used to > get threshould counter value. In Power10, the width of TECM field is > increase to 8bits. Patch fixes the current code to modify the MMCRA[TECM] > extraction macro to handling this changes. > > Fixes: 170a315f41c64 ('powerpc/perf: Support to export MMCRA[TEC*] field to userspace') > Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> > --- > arch/powerpc/perf/isa207-common.c | 3 +++ > arch/powerpc/perf/isa207-common.h | 4 ++++ > 2 files changed, 7 insertions(+) > > diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c > index 964437adec18..5fe129f02290 100644 > --- a/arch/powerpc/perf/isa207-common.c > +++ b/arch/powerpc/perf/isa207-common.c > @@ -247,6 +247,9 @@ void isa207_get_mem_weight(u64 *weight) > u64 sier = mfspr(SPRN_SIER); > u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; > > + if (cpu_has_feature(CPU_FTR_ARCH_31)) > + mantissa = P10_MMCRA_THR_CTR_MANT(mmcra); > + > if (val == 0 || val == 7) > *weight = 0; > else > diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h > index 044de65e96b9..71380e854f48 100644 > --- a/arch/powerpc/perf/isa207-common.h > +++ b/arch/powerpc/perf/isa207-common.h > @@ -219,6 +219,10 @@ > #define MMCRA_THR_CTR_EXP(v) (((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\ > MMCRA_THR_CTR_EXP_MASK) > > +#define P10_MMCRA_THR_CTR_MANT_MASK 0xFFul > +#define P10_MMCRA_THR_CTR_MANT(v) (((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\ > + P10_MMCRA_THR_CTR_MANT_MASK) > + > /* MMCRA Threshold Compare bit constant for power9 */ > #define p9_MMCRA_THR_CMP_SHIFT 45 > > -- > 2.26.2 >
On 10/12/20 4:59 PM, Michal Suchánek wrote: > Hello, > > On Mon, Oct 12, 2020 at 04:01:28PM +0530, Madhavan Srinivasan wrote: >> Power9 and isa v3.1 has 7bit mantissa field for Threshold Event Counter > ^^^ Shouldn't his be 3.0? My bad, What I meant was Power9, ISA v3.0 and ISA v3.1 define a 7 bit mantissa field for Threshold Event Counter Multiplier(TECM). Maddy > >> Multiplier (TECM). TECM is part of Monitor Mode Control Register A (MMCRA). >> This field along with Threshold Event Counter Exponent (TECE) is used to >> get threshould counter value. In Power10, the width of TECM field is >> increase to 8bits. Patch fixes the current code to modify the MMCRA[TECM] >> extraction macro to handling this changes. >> >> Fixes: 170a315f41c64 ('powerpc/perf: Support to export MMCRA[TEC*] field to userspace') >> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> >> --- >> arch/powerpc/perf/isa207-common.c | 3 +++ >> arch/powerpc/perf/isa207-common.h | 4 ++++ >> 2 files changed, 7 insertions(+) >> >> diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c >> index 964437adec18..5fe129f02290 100644 >> --- a/arch/powerpc/perf/isa207-common.c >> +++ b/arch/powerpc/perf/isa207-common.c >> @@ -247,6 +247,9 @@ void isa207_get_mem_weight(u64 *weight) >> u64 sier = mfspr(SPRN_SIER); >> u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; >> >> + if (cpu_has_feature(CPU_FTR_ARCH_31)) >> + mantissa = P10_MMCRA_THR_CTR_MANT(mmcra); >> + >> if (val == 0 || val == 7) >> *weight = 0; >> else >> diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h >> index 044de65e96b9..71380e854f48 100644 >> --- a/arch/powerpc/perf/isa207-common.h >> +++ b/arch/powerpc/perf/isa207-common.h >> @@ -219,6 +219,10 @@ >> #define MMCRA_THR_CTR_EXP(v) (((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\ >> MMCRA_THR_CTR_EXP_MASK) >> >> +#define P10_MMCRA_THR_CTR_MANT_MASK 0xFFul >> +#define P10_MMCRA_THR_CTR_MANT(v) (((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\ >> + P10_MMCRA_THR_CTR_MANT_MASK) >> + >> /* MMCRA Threshold Compare bit constant for power9 */ >> #define p9_MMCRA_THR_CMP_SHIFT 45 >> >> -- >> 2.26.2 >>
On Tue, Oct 13, 2020 at 06:27:05PM +0530, Madhavan Srinivasan wrote: > > On 10/12/20 4:59 PM, Michal Suchánek wrote: > > Hello, > > > > On Mon, Oct 12, 2020 at 04:01:28PM +0530, Madhavan Srinivasan wrote: > > > Power9 and isa v3.1 has 7bit mantissa field for Threshold Event Counter > > ^^^ Shouldn't his be 3.0? > > My bad, What I meant was > > Power9, ISA v3.0 and ISA v3.1 define a 7 bit mantissa field for Threshold > Event Counter Multiplier(TECM). I am really confused. The following text and the code suggests that the mantissa is 8bit on POWER10 and ISA v3.1. Thanks Michal > > Maddy > > > > > > Multiplier (TECM). TECM is part of Monitor Mode Control Register A (MMCRA). > > > This field along with Threshold Event Counter Exponent (TECE) is used to > > > get threshould counter value. In Power10, the width of TECM field is > > > increase to 8bits. Patch fixes the current code to modify the MMCRA[TECM] > > > extraction macro to handling this changes. > > > > > > Fixes: 170a315f41c64 ('powerpc/perf: Support to export MMCRA[TEC*] field to userspace') > > > Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> > > > --- > > > arch/powerpc/perf/isa207-common.c | 3 +++ > > > arch/powerpc/perf/isa207-common.h | 4 ++++ > > > 2 files changed, 7 insertions(+) > > > > > > diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c > > > index 964437adec18..5fe129f02290 100644 > > > --- a/arch/powerpc/perf/isa207-common.c > > > +++ b/arch/powerpc/perf/isa207-common.c > > > @@ -247,6 +247,9 @@ void isa207_get_mem_weight(u64 *weight) > > > u64 sier = mfspr(SPRN_SIER); > > > u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; > > > + if (cpu_has_feature(CPU_FTR_ARCH_31)) > > > + mantissa = P10_MMCRA_THR_CTR_MANT(mmcra); > > > + > > > if (val == 0 || val == 7) > > > *weight = 0; > > > else > > > diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h > > > index 044de65e96b9..71380e854f48 100644 > > > --- a/arch/powerpc/perf/isa207-common.h > > > +++ b/arch/powerpc/perf/isa207-common.h > > > @@ -219,6 +219,10 @@ > > > #define MMCRA_THR_CTR_EXP(v) (((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\ > > > MMCRA_THR_CTR_EXP_MASK) > > > +#define P10_MMCRA_THR_CTR_MANT_MASK 0xFFul > > > +#define P10_MMCRA_THR_CTR_MANT(v) (((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\ > > > + P10_MMCRA_THR_CTR_MANT_MASK) > > > + > > > /* MMCRA Threshold Compare bit constant for power9 */ > > > #define p9_MMCRA_THR_CMP_SHIFT 45 > > > -- > > > 2.26.2 > > >
On 10/13/20 9:28 PM, Michal Suchánek wrote: > On Tue, Oct 13, 2020 at 06:27:05PM +0530, Madhavan Srinivasan wrote: >> On 10/12/20 4:59 PM, Michal Suchánek wrote: >>> Hello, >>> >>> On Mon, Oct 12, 2020 at 04:01:28PM +0530, Madhavan Srinivasan wrote: >>>> Power9 and isa v3.1 has 7bit mantissa field for Threshold Event Counter >>> ^^^ Shouldn't his be 3.0? >> My bad, What I meant was >> >> Power9, ISA v3.0 and ISA v3.1 define a 7 bit mantissa field for Threshold >> Event Counter Multiplier(TECM). > I am really confused. > > The following text and the code suggests that the mantissa is 8bit on > POWER10 and ISA v3.1. Ok got it. Will fix the CPU_FTR_ARCH_31 check. Thanks for review Maddy > > Thanks > > Michal >> Maddy >> >>>> Multiplier (TECM). TECM is part of Monitor Mode Control Register A (MMCRA). >>>> This field along with Threshold Event Counter Exponent (TECE) is used to >>>> get threshould counter value. In Power10, the width of TECM field is >>>> increase to 8bits. Patch fixes the current code to modify the MMCRA[TECM] >>>> extraction macro to handling this changes. >>>> >>>> Fixes: 170a315f41c64 ('powerpc/perf: Support to export MMCRA[TEC*] field to userspace') >>>> Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> >>>> --- >>>> arch/powerpc/perf/isa207-common.c | 3 +++ >>>> arch/powerpc/perf/isa207-common.h | 4 ++++ >>>> 2 files changed, 7 insertions(+) >>>> >>>> diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c >>>> index 964437adec18..5fe129f02290 100644 >>>> --- a/arch/powerpc/perf/isa207-common.c >>>> +++ b/arch/powerpc/perf/isa207-common.c >>>> @@ -247,6 +247,9 @@ void isa207_get_mem_weight(u64 *weight) >>>> u64 sier = mfspr(SPRN_SIER); >>>> u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; >>>> + if (cpu_has_feature(CPU_FTR_ARCH_31)) >>>> + mantissa = P10_MMCRA_THR_CTR_MANT(mmcra); >>>> + >>>> if (val == 0 || val == 7) >>>> *weight = 0; >>>> else >>>> diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h >>>> index 044de65e96b9..71380e854f48 100644 >>>> --- a/arch/powerpc/perf/isa207-common.h >>>> +++ b/arch/powerpc/perf/isa207-common.h >>>> @@ -219,6 +219,10 @@ >>>> #define MMCRA_THR_CTR_EXP(v) (((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\ >>>> MMCRA_THR_CTR_EXP_MASK) >>>> +#define P10_MMCRA_THR_CTR_MANT_MASK 0xFFul >>>> +#define P10_MMCRA_THR_CTR_MANT(v) (((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\ >>>> + P10_MMCRA_THR_CTR_MANT_MASK) >>>> + >>>> /* MMCRA Threshold Compare bit constant for power9 */ >>>> #define p9_MMCRA_THR_CMP_SHIFT 45 >>>> -- >>>> 2.26.2 >>>>
diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c index 964437adec18..5fe129f02290 100644 --- a/arch/powerpc/perf/isa207-common.c +++ b/arch/powerpc/perf/isa207-common.c @@ -247,6 +247,9 @@ void isa207_get_mem_weight(u64 *weight) u64 sier = mfspr(SPRN_SIER); u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; + if (cpu_has_feature(CPU_FTR_ARCH_31)) + mantissa = P10_MMCRA_THR_CTR_MANT(mmcra); + if (val == 0 || val == 7) *weight = 0; else diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h index 044de65e96b9..71380e854f48 100644 --- a/arch/powerpc/perf/isa207-common.h +++ b/arch/powerpc/perf/isa207-common.h @@ -219,6 +219,10 @@ #define MMCRA_THR_CTR_EXP(v) (((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\ MMCRA_THR_CTR_EXP_MASK) +#define P10_MMCRA_THR_CTR_MANT_MASK 0xFFul +#define P10_MMCRA_THR_CTR_MANT(v) (((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\ + P10_MMCRA_THR_CTR_MANT_MASK) + /* MMCRA Threshold Compare bit constant for power9 */ #define p9_MMCRA_THR_CMP_SHIFT 45
Power9 and isa v3.1 has 7bit mantissa field for Threshold Event Counter Multiplier (TECM). TECM is part of Monitor Mode Control Register A (MMCRA). This field along with Threshold Event Counter Exponent (TECE) is used to get threshould counter value. In Power10, the width of TECM field is increase to 8bits. Patch fixes the current code to modify the MMCRA[TECM] extraction macro to handling this changes. Fixes: 170a315f41c64 ('powerpc/perf: Support to export MMCRA[TEC*] field to userspace') Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com> --- arch/powerpc/perf/isa207-common.c | 3 +++ arch/powerpc/perf/isa207-common.h | 4 ++++ 2 files changed, 7 insertions(+)