| Message ID | 20200811095441.7636-3-Zhiqiang.Hou@nxp.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | PCI: dwc: Add the multiple PF support for DWC and Layerscape | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch powerpc/merge (f04b169e953c4db1a3a3c1d23eea09c726f01ee5) |
| snowpatch_ozlabs/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 50 lines checked |
| snowpatch_ozlabs/needsstable | success | Patch has no Fixes tags |
On Tue, Aug 11, 2020 at 05:54:31PM +0800, Zhiqiang Hou wrote: > From: Xiaowei Bao <xiaowei.bao@nxp.com> > > Add the doorbell mode of MSI-X in DWC EP driver. > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> > Reviewed-by: Andrew Murray <andrew.murray@arm.com> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > --- > V7: > - Rebase the patch without functionality change. > > drivers/pci/controller/dwc/pcie-designware-ep.c | 14 ++++++++++++++ > drivers/pci/controller/dwc/pcie-designware.h | 12 ++++++++++++ > 2 files changed, 26 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > index e5bd3a5ef380..e76b504ed465 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > @@ -471,6 +471,20 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, > return 0; > } > > +int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no, return void. It never has an error. It could also just be an inline function. > + u16 interrupt_num) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > + u32 msg_data; > + > + msg_data = (func_no << PCIE_MSIX_DOORBELL_PF_SHIFT) | > + (interrupt_num - 1); > + > + dw_pcie_writel_dbi(pci, PCIE_MSIX_DOORBELL, msg_data); > + > + return 0; > +} > + > int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > u16 interrupt_num) > { > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 89f8271ec5ee..745b4938225a 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -97,6 +97,9 @@ > #define PCIE_MISC_CONTROL_1_OFF 0x8BC > #define PCIE_DBI_RO_WR_EN BIT(0) > > +#define PCIE_MSIX_DOORBELL 0x948 > +#define PCIE_MSIX_DOORBELL_PF_SHIFT 24 > + > #define PCIE_PL_CHK_REG_CONTROL_STATUS 0xB20 > #define PCIE_PL_CHK_REG_CHK_REG_START BIT(0) > #define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS BIT(1) > @@ -434,6 +437,8 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, > u8 interrupt_num); > int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > u16 interrupt_num); > +int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no, > + u16 interrupt_num); > void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar); > #else > static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) > @@ -475,6 +480,13 @@ static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > return 0; > } > > +static inline int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, > + u8 func_no, > + u16 interrupt_num) > +{ > + return 0; > +} > + > static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) > { > } > -- > 2.17.1 >
Hi Rob, Thanks a lot for your comments! > -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: 2020年9月11日 1:58 > To: Z.q. Hou <zhiqiang.hou@nxp.com> > Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; > linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > linuxppc-dev@lists.ozlabs.org; bhelgaas@google.com; > lorenzo.pieralisi@arm.com; shawnguo@kernel.org; Leo Li > <leoyang.li@nxp.com>; kishon@ti.com; gustavo.pimentel@synopsys.com; > Roy Zang <roy.zang@nxp.com>; jingoohan1@gmail.com; > andrew.murray@arm.com; Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian > <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com> > Subject: Re: [PATCHv7 02/12] PCI: designware-ep: Add the doorbell mode of > MSI-X in EP mode > > On Tue, Aug 11, 2020 at 05:54:31PM +0800, Zhiqiang Hou wrote: > > From: Xiaowei Bao <xiaowei.bao@nxp.com> > > > > Add the doorbell mode of MSI-X in DWC EP driver. > > > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> > > Reviewed-by: Andrew Murray <andrew.murray@arm.com> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > --- > > V7: > > - Rebase the patch without functionality change. > > > > drivers/pci/controller/dwc/pcie-designware-ep.c | 14 ++++++++++++++ > > drivers/pci/controller/dwc/pcie-designware.h | 12 ++++++++++++ > > 2 files changed, 26 insertions(+) > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c > > b/drivers/pci/controller/dwc/pcie-designware-ep.c > > index e5bd3a5ef380..e76b504ed465 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > > @@ -471,6 +471,20 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep > *ep, u8 func_no, > > return 0; > > } > > > > +int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 > > +func_no, > > return void. It never has an error. > > It could also just be an inline function. Yes, make sense and will change in next version. Thanks, Zhiqiang > > > + u16 interrupt_num) > > +{ > > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > > + u32 msg_data; > > + > > + msg_data = (func_no << PCIE_MSIX_DOORBELL_PF_SHIFT) | > > + (interrupt_num - 1); > > + > > + dw_pcie_writel_dbi(pci, PCIE_MSIX_DOORBELL, msg_data); > > + > > + return 0; > > +} > > + > > int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > > u16 interrupt_num) > > { > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h > > b/drivers/pci/controller/dwc/pcie-designware.h > > index 89f8271ec5ee..745b4938225a 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.h > > +++ b/drivers/pci/controller/dwc/pcie-designware.h > > @@ -97,6 +97,9 @@ > > #define PCIE_MISC_CONTROL_1_OFF 0x8BC > > #define PCIE_DBI_RO_WR_EN BIT(0) > > > > +#define PCIE_MSIX_DOORBELL 0x948 > > +#define PCIE_MSIX_DOORBELL_PF_SHIFT 24 > > + > > #define PCIE_PL_CHK_REG_CONTROL_STATUS 0xB20 > > #define PCIE_PL_CHK_REG_CHK_REG_START BIT(0) > > #define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS BIT(1) > > @@ -434,6 +437,8 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep > *ep, u8 func_no, > > u8 interrupt_num); > > int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, > > u16 interrupt_num); > > +int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 > func_no, > > + u16 interrupt_num); > > void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar); > > #else static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) @@ > > -475,6 +480,13 @@ static inline int dw_pcie_ep_raise_msix_irq(struct > dw_pcie_ep *ep, u8 func_no, > > return 0; > > } > > > > +static inline int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep > *ep, > > + u8 func_no, > > + u16 interrupt_num) > > +{ > > + return 0; > > +} > > + > > static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum > > pci_barno bar) { } > > -- > > 2.17.1 > >
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index e5bd3a5ef380..e76b504ed465 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -471,6 +471,20 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, return 0; } +int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no, + u16 interrupt_num) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + u32 msg_data; + + msg_data = (func_no << PCIE_MSIX_DOORBELL_PF_SHIFT) | + (interrupt_num - 1); + + dw_pcie_writel_dbi(pci, PCIE_MSIX_DOORBELL, msg_data); + + return 0; +} + int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, u16 interrupt_num) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 89f8271ec5ee..745b4938225a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -97,6 +97,9 @@ #define PCIE_MISC_CONTROL_1_OFF 0x8BC #define PCIE_DBI_RO_WR_EN BIT(0) +#define PCIE_MSIX_DOORBELL 0x948 +#define PCIE_MSIX_DOORBELL_PF_SHIFT 24 + #define PCIE_PL_CHK_REG_CONTROL_STATUS 0xB20 #define PCIE_PL_CHK_REG_CHK_REG_START BIT(0) #define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS BIT(1) @@ -434,6 +437,8 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, u8 interrupt_num); int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, u16 interrupt_num); +int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no, + u16 interrupt_num); void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar); #else static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) @@ -475,6 +480,13 @@ static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, return 0; } +static inline int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, + u8 func_no, + u16 interrupt_num) +{ + return 0; +} + static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) { }