| Message ID | 20200710052340.737567-9-oohall@gmail.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [01/15] powernv/pci: Add pci_bus_to_pnvhb() helper | expand |
On 10/07/2020 15:23, Oliver O'Halloran wrote: > No need for the multi-dimensional arrays, just use a bitmap. > > Signed-off-by: Oliver O'Halloran <oohall@gmail.com> > --- > arch/powerpc/platforms/powernv/pci-sriov.c | 48 +++++++--------------- > arch/powerpc/platforms/powernv/pci.h | 7 +++- > 2 files changed, 20 insertions(+), 35 deletions(-) > > diff --git a/arch/powerpc/platforms/powernv/pci-sriov.c b/arch/powerpc/platforms/powernv/pci-sriov.c > index 216ceeff69b0..e4c65cb49757 100644 > --- a/arch/powerpc/platforms/powernv/pci-sriov.c > +++ b/arch/powerpc/platforms/powernv/pci-sriov.c > @@ -303,28 +303,20 @@ static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) > { > struct pnv_iov_data *iov; > struct pnv_phb *phb; > - int i, j; > - int m64_bars; > + int window_id; > > phb = pci_bus_to_pnvhb(pdev->bus); > iov = pnv_iov_get(pdev); > > - if (iov->m64_single_mode) > - m64_bars = num_vfs; > - else > - m64_bars = 1; > + for_each_set_bit(window_id, iov->used_m64_bar_mask, 64) { > + opal_pci_phb_mmio_enable(phb->opal_id, > + OPAL_M64_WINDOW_TYPE, > + window_id, > + 0); > > - for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) > - for (j = 0; j < m64_bars; j++) { > - if (iov->m64_map[j][i] == IODA_INVALID_M64) > - continue; > - opal_pci_phb_mmio_enable(phb->opal_id, > - OPAL_M64_WINDOW_TYPE, iov->m64_map[j][i], 0); > - clear_bit(iov->m64_map[j][i], &phb->ioda.m64_bar_alloc); > - iov->m64_map[j][i] = IODA_INVALID_M64; > - } > + clear_bit(window_id, &phb->ioda.m64_bar_alloc); > + } > > - kfree(iov->m64_map); > return 0; > } > > @@ -350,23 +342,14 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) > else > m64_bars = 1; > > - iov->m64_map = kmalloc_array(m64_bars, > - sizeof(*iov->m64_map), > - GFP_KERNEL); > - if (!iov->m64_map) > - return -ENOMEM; > - /* Initialize the m64_map to IODA_INVALID_M64 */ > - for (i = 0; i < m64_bars ; i++) > - for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) > - iov->m64_map[i][j] = IODA_INVALID_M64; > - > - > for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { > res = &pdev->resource[i + PCI_IOV_RESOURCES]; > if (!res->flags || !res->parent) > continue; > > for (j = 0; j < m64_bars; j++) { > + > + /* allocate a window ID for this BAR */ > do { > win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, > phb->ioda.m64_bar_idx + 1, 0); > @@ -374,8 +357,7 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) > if (win >= phb->ioda.m64_bar_idx + 1) > goto m64_failed; > } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); > - > - iov->m64_map[j][i] = win; > + set_bit(win, iov->used_m64_bar_mask); > > if (iov->m64_single_mode) { > size = pci_iov_resource_size(pdev, > @@ -391,12 +373,12 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) > pe_num = iov->pe_num_map[j]; > rc = opal_pci_map_pe_mmio_window(phb->opal_id, > pe_num, OPAL_M64_WINDOW_TYPE, > - iov->m64_map[j][i], 0); > + win, 0); > } > > rc = opal_pci_set_phb_mem_window(phb->opal_id, > OPAL_M64_WINDOW_TYPE, > - iov->m64_map[j][i], > + win, > start, > 0, /* unused */ > size); > @@ -410,10 +392,10 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) > > if (iov->m64_single_mode) > rc = opal_pci_phb_mmio_enable(phb->opal_id, > - OPAL_M64_WINDOW_TYPE, iov->m64_map[j][i], 2); > + OPAL_M64_WINDOW_TYPE, win, 2); > else > rc = opal_pci_phb_mmio_enable(phb->opal_id, > - OPAL_M64_WINDOW_TYPE, iov->m64_map[j][i], 1); > + OPAL_M64_WINDOW_TYPE, win, 1); > > if (rc != OPAL_SUCCESS) { > dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", > diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h > index 0156d7d17f7d..58c97e60c3db 100644 > --- a/arch/powerpc/platforms/powernv/pci.h > +++ b/arch/powerpc/platforms/powernv/pci.h > @@ -243,8 +243,11 @@ struct pnv_iov_data { > /* Did we map the VF BARs with single-PE IODA BARs? */ > bool m64_single_mode; > > - int (*m64_map)[PCI_SRIOV_NUM_BARS]; > -#define IODA_INVALID_M64 (-1) > + /* > + * Bit mask used to track which m64 windows that we used to map the Language question: either "which" or "that" but both? > + * SR-IOV BARs for this device. > + */ > + DECLARE_BITMAP(used_m64_bar_mask, 64); 64 here is the maximum number of M64's (which is 16 at the moment)? Can we define this 64 somehow (appears twice in this patch alone)? Anyway, the change is correct. Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> > > /* > * If we map the SR-IOV BARs with a segmented window then >
On Wed, Jul 15, 2020 at 11:34 AM Alexey Kardashevskiy <aik@ozlabs.ru> wrote: > > On 10/07/2020 15:23, Oliver O'Halloran wrote: > > diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h > > index 0156d7d17f7d..58c97e60c3db 100644 > > --- a/arch/powerpc/platforms/powernv/pci.h > > +++ b/arch/powerpc/platforms/powernv/pci.h > > @@ -243,8 +243,11 @@ struct pnv_iov_data { > > /* Did we map the VF BARs with single-PE IODA BARs? */ > > bool m64_single_mode; > > > > - int (*m64_map)[PCI_SRIOV_NUM_BARS]; > > -#define IODA_INVALID_M64 (-1) > > + /* > > + * Bit mask used to track which m64 windows that we used to map the > > > Language question: either "which" or "that" but both? Uhhhh... I don't speak english
diff --git a/arch/powerpc/platforms/powernv/pci-sriov.c b/arch/powerpc/platforms/powernv/pci-sriov.c index 216ceeff69b0..e4c65cb49757 100644 --- a/arch/powerpc/platforms/powernv/pci-sriov.c +++ b/arch/powerpc/platforms/powernv/pci-sriov.c @@ -303,28 +303,20 @@ static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) { struct pnv_iov_data *iov; struct pnv_phb *phb; - int i, j; - int m64_bars; + int window_id; phb = pci_bus_to_pnvhb(pdev->bus); iov = pnv_iov_get(pdev); - if (iov->m64_single_mode) - m64_bars = num_vfs; - else - m64_bars = 1; + for_each_set_bit(window_id, iov->used_m64_bar_mask, 64) { + opal_pci_phb_mmio_enable(phb->opal_id, + OPAL_M64_WINDOW_TYPE, + window_id, + 0); - for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) - for (j = 0; j < m64_bars; j++) { - if (iov->m64_map[j][i] == IODA_INVALID_M64) - continue; - opal_pci_phb_mmio_enable(phb->opal_id, - OPAL_M64_WINDOW_TYPE, iov->m64_map[j][i], 0); - clear_bit(iov->m64_map[j][i], &phb->ioda.m64_bar_alloc); - iov->m64_map[j][i] = IODA_INVALID_M64; - } + clear_bit(window_id, &phb->ioda.m64_bar_alloc); + } - kfree(iov->m64_map); return 0; } @@ -350,23 +342,14 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) else m64_bars = 1; - iov->m64_map = kmalloc_array(m64_bars, - sizeof(*iov->m64_map), - GFP_KERNEL); - if (!iov->m64_map) - return -ENOMEM; - /* Initialize the m64_map to IODA_INVALID_M64 */ - for (i = 0; i < m64_bars ; i++) - for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) - iov->m64_map[i][j] = IODA_INVALID_M64; - - for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { res = &pdev->resource[i + PCI_IOV_RESOURCES]; if (!res->flags || !res->parent) continue; for (j = 0; j < m64_bars; j++) { + + /* allocate a window ID for this BAR */ do { win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, phb->ioda.m64_bar_idx + 1, 0); @@ -374,8 +357,7 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) if (win >= phb->ioda.m64_bar_idx + 1) goto m64_failed; } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); - - iov->m64_map[j][i] = win; + set_bit(win, iov->used_m64_bar_mask); if (iov->m64_single_mode) { size = pci_iov_resource_size(pdev, @@ -391,12 +373,12 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) pe_num = iov->pe_num_map[j]; rc = opal_pci_map_pe_mmio_window(phb->opal_id, pe_num, OPAL_M64_WINDOW_TYPE, - iov->m64_map[j][i], 0); + win, 0); } rc = opal_pci_set_phb_mem_window(phb->opal_id, OPAL_M64_WINDOW_TYPE, - iov->m64_map[j][i], + win, start, 0, /* unused */ size); @@ -410,10 +392,10 @@ static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) if (iov->m64_single_mode) rc = opal_pci_phb_mmio_enable(phb->opal_id, - OPAL_M64_WINDOW_TYPE, iov->m64_map[j][i], 2); + OPAL_M64_WINDOW_TYPE, win, 2); else rc = opal_pci_phb_mmio_enable(phb->opal_id, - OPAL_M64_WINDOW_TYPE, iov->m64_map[j][i], 1); + OPAL_M64_WINDOW_TYPE, win, 1); if (rc != OPAL_SUCCESS) { dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h index 0156d7d17f7d..58c97e60c3db 100644 --- a/arch/powerpc/platforms/powernv/pci.h +++ b/arch/powerpc/platforms/powernv/pci.h @@ -243,8 +243,11 @@ struct pnv_iov_data { /* Did we map the VF BARs with single-PE IODA BARs? */ bool m64_single_mode; - int (*m64_map)[PCI_SRIOV_NUM_BARS]; -#define IODA_INVALID_M64 (-1) + /* + * Bit mask used to track which m64 windows that we used to map the + * SR-IOV BARs for this device. + */ + DECLARE_BITMAP(used_m64_bar_mask, 64); /* * If we map the SR-IOV BARs with a segmented window then
No need for the multi-dimensional arrays, just use a bitmap. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> --- arch/powerpc/platforms/powernv/pci-sriov.c | 48 +++++++--------------- arch/powerpc/platforms/powernv/pci.h | 7 +++- 2 files changed, 20 insertions(+), 35 deletions(-)