| Message ID | 20200525025923.19843-5-jniethe5@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 4f825900786e1c24e4c48622e12eb493a6cd27b6 |
| Headers | show |
| Series | [1/5] powerpc sstep: Add tests for prefixed integer load/stores | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch powerpc/merge (1ef93962cf4293ec9e1bb3163cc4b7dcfc3de84f) |
| snowpatch_ozlabs/build-ppc64le | success | Build succeeded |
| snowpatch_ozlabs/build-ppc64be | success | Build succeeded |
| snowpatch_ozlabs/build-ppc64e | success | Build succeeded |
| snowpatch_ozlabs/build-pmac32 | success | Build succeeded |
| snowpatch_ozlabs/checkpatch | warning | total: 0 errors, 0 warnings, 1 checks, 152 lines checked |
| snowpatch_ozlabs/needsstable | success | Patch has no Fixes tags |
On Mon, May 25, 2020 at 1:00 PM Jordan Niethe <jniethe5@gmail.com> wrote: > > Use the existing support for testing compute type instructions to test > Prefixed Add Immediate (paddi). The R bit of the paddi instruction > controls whether current instruction address is used. Add test cases for > when R=1 and for R=0. paddi has a 34 bit immediate field formed by > concatenating si0 and si1. Add tests for the extreme values of this > field. > > Skip the paddi tests if ISA v3.1 is unsupported. > > Some of these test cases were added by Balamuruhan S. > > Signed-off-by: Jordan Niethe <jniethe5@gmail.com> > --- > arch/powerpc/lib/test_emulate_step.c | 127 ++++++++++++++++++ > .../lib/test_emulate_step_exec_instr.S | 1 + > 2 files changed, 128 insertions(+) > > diff --git a/arch/powerpc/lib/test_emulate_step.c b/arch/powerpc/lib/test_emulate_step.c > index 579b5db80674..33a72b7d2764 100644 > --- a/arch/powerpc/lib/test_emulate_step.c > +++ b/arch/powerpc/lib/test_emulate_step.c > @@ -105,6 +105,13 @@ > ___PPC_RA(a) | ___PPC_RB(b)) > #define TEST_ADDC_DOT(t, a, b) ppc_inst(PPC_INST_ADDC | ___PPC_RT(t) | \ > ___PPC_RA(a) | ___PPC_RB(b) | 0x1) > +#define TEST_PADDI(t, a, i, pr) ppc_inst_prefix(PPC_PREFIX_MLS | __PPC_PRFX_R(pr) | \ > + IMM_H(i), \ > + PPC_INST_ADDI | \ > + ___PPC_RT(t) | ___PPC_RA(a) | \ > + IMM_L(i)) > + > + > > #define MAX_SUBTESTS 16 > > @@ -699,6 +706,11 @@ struct compute_test { > } subtests[MAX_SUBTESTS + 1]; > }; > > +/* Extreme values for si0||si1 (the MLS:D-form 34 bit immediate field) */ > +#define SI_MIN BIT(33) > +#define SI_MAX (BIT(33) - 1) > +#define SI_UMAX (BIT(34) - 1) > + > static struct compute_test compute_tests[] = { > { > .mnemonic = "nop", > @@ -1071,6 +1083,121 @@ static struct compute_test compute_tests[] = { > } > } > } > + }, > + { > + .mnemonic = "paddi", > + .cpu_feature = CPU_FTR_ARCH_31, > + .subtests = { > + { > + .descr = "RA = LONG_MIN, SI = SI_MIN, R = 0", > + .instr = TEST_PADDI(21, 22, SI_MIN, 0), > + .regs = { > + .gpr[21] = 0, > + .gpr[22] = LONG_MIN, > + } > + }, > + { > + .descr = "RA = LONG_MIN, SI = SI_MAX, R = 0", > + .instr = TEST_PADDI(21, 22, SI_MAX, 0), > + .regs = { > + .gpr[21] = 0, > + .gpr[22] = LONG_MIN, > + } > + }, > + { > + .descr = "RA = LONG_MAX, SI = SI_MAX, R = 0", > + .instr = TEST_PADDI(21, 22, SI_MAX, 0), > + .regs = { > + .gpr[21] = 0, > + .gpr[22] = LONG_MAX, > + } > + }, > + { > + .descr = "RA = ULONG_MAX, SI = SI_UMAX, R = 0", > + .instr = TEST_PADDI(21, 22, SI_UMAX, 0), > + .regs = { > + .gpr[21] = 0, > + .gpr[22] = ULONG_MAX, > + } > + }, > + { > + .descr = "RA = ULONG_MAX, SI = 0x1, R = 0", > + .instr = TEST_PADDI(21, 22, 0x1, 0), > + .regs = { > + .gpr[21] = 0, > + .gpr[22] = ULONG_MAX, > + } > + }, > + { > + .descr = "RA = INT_MIN, SI = SI_MIN, R = 0", > + .instr = TEST_PADDI(21, 22, SI_MIN, 0), > + .regs = { > + .gpr[21] = 0, > + .gpr[22] = INT_MIN, > + } > + }, > + { > + .descr = "RA = INT_MIN, SI = SI_MAX, R = 0", > + .instr = TEST_PADDI(21, 22, SI_MAX, 0), > + .regs = { > + .gpr[21] = 0, > + .gpr[22] = INT_MIN, > + } > + }, > + { > + .descr = "RA = INT_MAX, SI = SI_MAX, R = 0", > + .instr = TEST_PADDI(21, 22, SI_MAX, 0), > + .regs = { > + .gpr[21] = 0, > + .gpr[22] = INT_MAX, > + } > + }, > + { > + .descr = "RA = UINT_MAX, SI = 0x1, R = 0", > + .instr = TEST_PADDI(21, 22, 0x1, 0), > + .regs = { > + .gpr[21] = 0, > + .gpr[22] = UINT_MAX, > + } > + }, > + { > + .descr = "RA = UINT_MAX, SI = SI_MAX, R = 0", > + .instr = TEST_PADDI(21, 22, SI_MAX, 0), > + .regs = { > + .gpr[21] = 0, > + .gpr[22] = UINT_MAX, > + } > + }, > + { > + .descr = "RA is r0, SI = SI_MIN, R = 0", > + .instr = TEST_PADDI(21, 0, SI_MIN, 0), > + .regs = { > + .gpr[21] = 0x0, > + } > + }, > + { > + .descr = "RA = 0, SI = SI_MIN, R = 0", > + .instr = TEST_PADDI(21, 22, SI_MIN, 0), > + .regs = { > + .gpr[21] = 0x0, > + .gpr[22] = 0x0, > + } > + }, > + { > + .descr = "RA is r0, SI = 0, R = 1", > + .instr = TEST_PADDI(21, 0, 0, 1), > + .regs = { > + .gpr[21] = 0, > + } > + }, > + { > + .descr = "RA is r0, SI = SI_MIN, R = 1", > + .instr = TEST_PADDI(21, 0, SI_MIN, 1), > + .regs = { > + .gpr[21] = 0, > + } > + } > + } > } > }; > > diff --git a/arch/powerpc/lib/test_emulate_step_exec_instr.S b/arch/powerpc/lib/test_emulate_step_exec_instr.S > index 1580f34f4f4f..aef53ee77a43 100644 > --- a/arch/powerpc/lib/test_emulate_step_exec_instr.S > +++ b/arch/powerpc/lib/test_emulate_step_exec_instr.S > @@ -81,6 +81,7 @@ _GLOBAL(exec_instr) > > /* Placeholder for the test instruction */ > 1: nop > + nop > patch_site 1b patch__exec_instr > > /* > -- > 2.17.1 > Because of the alignment requirements of prefixed instructions, the noops to be patched need to be aligned. mpe, want me to send a new version? --- a/arch/powerpc/lib/test_emulate_step_exec_instr.S +++ b/arch/powerpc/lib/test_emulate_step_exec_instr.S @@ -80,6 +80,7 @@ _GLOBAL(exec_instr) REST_NVGPRS(r31) /* Placeholder for the test instruction */ +.align 6 1: nop nop patch_site 1b patch__exec_instr
Jordan Niethe <jniethe5@gmail.com> writes: > On Mon, May 25, 2020 at 1:00 PM Jordan Niethe <jniethe5@gmail.com> wrote: >> >> Use the existing support for testing compute type instructions to test >> Prefixed Add Immediate (paddi). The R bit of the paddi instruction >> controls whether current instruction address is used. Add test cases for >> when R=1 and for R=0. paddi has a 34 bit immediate field formed by >> concatenating si0 and si1. Add tests for the extreme values of this >> field. >> >> Skip the paddi tests if ISA v3.1 is unsupported. >> >> Some of these test cases were added by Balamuruhan S. >> >> Signed-off-by: Jordan Niethe <jniethe5@gmail.com> >> --- >> arch/powerpc/lib/test_emulate_step.c | 127 ++++++++++++++++++ >> .../lib/test_emulate_step_exec_instr.S | 1 + >> 2 files changed, 128 insertions(+) ... >> diff --git a/arch/powerpc/lib/test_emulate_step_exec_instr.S b/arch/powerpc/lib/test_emulate_step_exec_instr.S >> index 1580f34f4f4f..aef53ee77a43 100644 >> --- a/arch/powerpc/lib/test_emulate_step_exec_instr.S >> +++ b/arch/powerpc/lib/test_emulate_step_exec_instr.S >> @@ -81,6 +81,7 @@ _GLOBAL(exec_instr) >> >> /* Placeholder for the test instruction */ >> 1: nop >> + nop >> patch_site 1b patch__exec_instr >> >> /* >> -- >> 2.17.1 >> > > Because of the alignment requirements of prefixed instructions, the > noops to be patched need to be aligned. > mpe, want me to send a new version? No I'll just squash it in. > --- a/arch/powerpc/lib/test_emulate_step_exec_instr.S > +++ b/arch/powerpc/lib/test_emulate_step_exec_instr.S > @@ -80,6 +80,7 @@ _GLOBAL(exec_instr) > REST_NVGPRS(r31) > > /* Placeholder for the test instruction */ > +.align 6 I'll change it to .balign 64. > 1: nop > nop > patch_site 1b patch__exec_instr cheers
diff --git a/arch/powerpc/lib/test_emulate_step.c b/arch/powerpc/lib/test_emulate_step.c index 579b5db80674..33a72b7d2764 100644 --- a/arch/powerpc/lib/test_emulate_step.c +++ b/arch/powerpc/lib/test_emulate_step.c @@ -105,6 +105,13 @@ ___PPC_RA(a) | ___PPC_RB(b)) #define TEST_ADDC_DOT(t, a, b) ppc_inst(PPC_INST_ADDC | ___PPC_RT(t) | \ ___PPC_RA(a) | ___PPC_RB(b) | 0x1) +#define TEST_PADDI(t, a, i, pr) ppc_inst_prefix(PPC_PREFIX_MLS | __PPC_PRFX_R(pr) | \ + IMM_H(i), \ + PPC_INST_ADDI | \ + ___PPC_RT(t) | ___PPC_RA(a) | \ + IMM_L(i)) + + #define MAX_SUBTESTS 16 @@ -699,6 +706,11 @@ struct compute_test { } subtests[MAX_SUBTESTS + 1]; }; +/* Extreme values for si0||si1 (the MLS:D-form 34 bit immediate field) */ +#define SI_MIN BIT(33) +#define SI_MAX (BIT(33) - 1) +#define SI_UMAX (BIT(34) - 1) + static struct compute_test compute_tests[] = { { .mnemonic = "nop", @@ -1071,6 +1083,121 @@ static struct compute_test compute_tests[] = { } } } + }, + { + .mnemonic = "paddi", + .cpu_feature = CPU_FTR_ARCH_31, + .subtests = { + { + .descr = "RA = LONG_MIN, SI = SI_MIN, R = 0", + .instr = TEST_PADDI(21, 22, SI_MIN, 0), + .regs = { + .gpr[21] = 0, + .gpr[22] = LONG_MIN, + } + }, + { + .descr = "RA = LONG_MIN, SI = SI_MAX, R = 0", + .instr = TEST_PADDI(21, 22, SI_MAX, 0), + .regs = { + .gpr[21] = 0, + .gpr[22] = LONG_MIN, + } + }, + { + .descr = "RA = LONG_MAX, SI = SI_MAX, R = 0", + .instr = TEST_PADDI(21, 22, SI_MAX, 0), + .regs = { + .gpr[21] = 0, + .gpr[22] = LONG_MAX, + } + }, + { + .descr = "RA = ULONG_MAX, SI = SI_UMAX, R = 0", + .instr = TEST_PADDI(21, 22, SI_UMAX, 0), + .regs = { + .gpr[21] = 0, + .gpr[22] = ULONG_MAX, + } + }, + { + .descr = "RA = ULONG_MAX, SI = 0x1, R = 0", + .instr = TEST_PADDI(21, 22, 0x1, 0), + .regs = { + .gpr[21] = 0, + .gpr[22] = ULONG_MAX, + } + }, + { + .descr = "RA = INT_MIN, SI = SI_MIN, R = 0", + .instr = TEST_PADDI(21, 22, SI_MIN, 0), + .regs = { + .gpr[21] = 0, + .gpr[22] = INT_MIN, + } + }, + { + .descr = "RA = INT_MIN, SI = SI_MAX, R = 0", + .instr = TEST_PADDI(21, 22, SI_MAX, 0), + .regs = { + .gpr[21] = 0, + .gpr[22] = INT_MIN, + } + }, + { + .descr = "RA = INT_MAX, SI = SI_MAX, R = 0", + .instr = TEST_PADDI(21, 22, SI_MAX, 0), + .regs = { + .gpr[21] = 0, + .gpr[22] = INT_MAX, + } + }, + { + .descr = "RA = UINT_MAX, SI = 0x1, R = 0", + .instr = TEST_PADDI(21, 22, 0x1, 0), + .regs = { + .gpr[21] = 0, + .gpr[22] = UINT_MAX, + } + }, + { + .descr = "RA = UINT_MAX, SI = SI_MAX, R = 0", + .instr = TEST_PADDI(21, 22, SI_MAX, 0), + .regs = { + .gpr[21] = 0, + .gpr[22] = UINT_MAX, + } + }, + { + .descr = "RA is r0, SI = SI_MIN, R = 0", + .instr = TEST_PADDI(21, 0, SI_MIN, 0), + .regs = { + .gpr[21] = 0x0, + } + }, + { + .descr = "RA = 0, SI = SI_MIN, R = 0", + .instr = TEST_PADDI(21, 22, SI_MIN, 0), + .regs = { + .gpr[21] = 0x0, + .gpr[22] = 0x0, + } + }, + { + .descr = "RA is r0, SI = 0, R = 1", + .instr = TEST_PADDI(21, 0, 0, 1), + .regs = { + .gpr[21] = 0, + } + }, + { + .descr = "RA is r0, SI = SI_MIN, R = 1", + .instr = TEST_PADDI(21, 0, SI_MIN, 1), + .regs = { + .gpr[21] = 0, + } + } + } } }; diff --git a/arch/powerpc/lib/test_emulate_step_exec_instr.S b/arch/powerpc/lib/test_emulate_step_exec_instr.S index 1580f34f4f4f..aef53ee77a43 100644 --- a/arch/powerpc/lib/test_emulate_step_exec_instr.S +++ b/arch/powerpc/lib/test_emulate_step_exec_instr.S @@ -81,6 +81,7 @@ _GLOBAL(exec_instr) /* Placeholder for the test instruction */ 1: nop + nop patch_site 1b patch__exec_instr /*
Use the existing support for testing compute type instructions to test Prefixed Add Immediate (paddi). The R bit of the paddi instruction controls whether current instruction address is used. Add test cases for when R=1 and for R=0. paddi has a 34 bit immediate field formed by concatenating si0 and si1. Add tests for the extreme values of this field. Skip the paddi tests if ISA v3.1 is unsupported. Some of these test cases were added by Balamuruhan S. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> --- arch/powerpc/lib/test_emulate_step.c | 127 ++++++++++++++++++ .../lib/test_emulate_step_exec_instr.S | 1 + 2 files changed, 128 insertions(+)