| Message ID | 20191218043048.3400-2-sukadev@linux.ibm.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [1/2] powerpc/pseries/svm: Don't access some SPRs | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch powerpc/merge (270c0c3e491684893e7250f6c32f4f2eb2e4c3b2) |
| snowpatch_ozlabs/build-ppc64le | success | Build succeeded |
| snowpatch_ozlabs/build-ppc64be | success | Build succeeded |
| snowpatch_ozlabs/build-ppc64e | success | Build succeeded |
| snowpatch_ozlabs/build-pmac32 | success | Build succeeded |
| snowpatch_ozlabs/checkpatch | warning | total: 0 errors, 1 warnings, 0 checks, 48 lines checked |
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index a460298c7ddb..d5eb06e20b5a 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S @@ -206,14 +206,36 @@ __init_PMU_HV_ISA207: blr __init_PMU: +#ifdef CONFIG_PPC_SVM + /* + * For now, SVM's are restricted from accessing PMU + * features, so skip accordingly. + */ + mfmsr r5 + rldicl r5, r5, 64-MSR_S_LG, 62 + cmpwi r5,1 + beq skip1 +#endif li r5,0 mtspr SPRN_MMCRA,r5 mtspr SPRN_MMCR0,r5 mtspr SPRN_MMCR1,r5 mtspr SPRN_MMCR2,r5 +skip1: blr __init_PMU_ISA207: +#ifdef CONFIG_PPC_SVM + /* + * For now, SVM's are restricted from accessing PMU + * features, so skip accordingly. + */ + mfmsr r5 + rldicl r5, r5, 64-MSR_S_LG, 62 + cmpwi r5,1 + beq skip2 +#endif li r5,0 mtspr SPRN_MMCRS,r5 +skip2: blr diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 4e76b2251801..9e6a9f1803f6 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -2275,6 +2275,12 @@ static int power_pmu_prepare_cpu(unsigned int cpu) int register_power_pmu(struct power_pmu *pmu) { + /* + * PMU events are not currently supported in SVMs + */ + if (is_secure_guest()) + return -ENOSYS; + if (ppmu) return -EBUSY; /* something's already registered */
For now, disable hardware PMU facilities in secure virtual machines (SVMs) to prevent any information leak between SVMs and the (untrusted) HV. With this, a simple 'myperf' program that uses the perf_event_open() fails for SVMs (with the corresponding fix to UV). In normal VMs and on the bare-metal HV the syscall and performance counters work Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.ibm.com> --- arch/powerpc/kernel/cpu_setup_power.S | 22 ++++++++++++++++++++++ arch/powerpc/perf/core-book3s.c | 6 ++++++ 2 files changed, 28 insertions(+)