From patchwork Tue Jun 19 16:22:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joakim Tjernlund X-Patchwork-Id: 931741 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 419D6y6MzGz9s3R for ; Wed, 20 Jun 2018 02:33:46 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=infinera.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 419D6y5DWMzF0tm for ; Wed, 20 Jun 2018 02:33:46 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=infinera.com X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=infinera.com (client-ip=31.15.61.139; helo=smtp.transmode.se; envelope-from=joakim.tjernlund@infinera.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=infinera.com X-Greylist: delayed 493 seconds by postgrey-1.36 at bilbo; Wed, 20 Jun 2018 02:30:41 AEST Received: from smtp.transmode.se (smtp.transmode.se [31.15.61.139]) by lists.ozlabs.org (Postfix) with ESMTP id 419D3P29FVzF0wQ for ; Wed, 20 Jun 2018 02:30:41 +1000 (AEST) Received: from gentoo-jocke.infinera.com (gentoo-jocke.infinera.com [10.210.72.209]) by smtp.transmode.se (Postfix) with ESMTP id B4625118ACF9; Tue, 19 Jun 2018 18:22:19 +0200 (CEST) Received: from gentoo-jocke.infinera.com (gentoo-jocke.infinera.com [127.0.0.1]) by gentoo-jocke.infinera.com (8.14.9/8.14.9) with ESMTP id w5JGMJpD020120; Tue, 19 Jun 2018 18:22:19 +0200 Received: (from jocke@localhost) by gentoo-jocke.infinera.com (8.14.9/8.14.9/Submit) id w5JGMJ3D020119; Tue, 19 Jun 2018 18:22:19 +0200 From: Joakim Tjernlund To: York Sun , linuxppc-dev Subject: [PATCH] QE GPIO: Add qe_gpio_set_multiple Date: Tue, 19 Jun 2018 18:22:16 +0200 Message-Id: <20180619162216.20030-1-joakim.tjernlund@infinera.com> X-Mailer: git-send-email 2.13.6 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" This cousin to gpio-mpc8xxx was lacking a multiple pins method, add one. Signed-off-by: Joakim Tjernlund Signed-off-by: Joakim Tjernlund Reviewed-by: Qiang Zhao --- drivers/soc/fsl/qe/gpio.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index 3b27075c21a7..819bed0f5667 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -83,6 +83,33 @@ static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) spin_unlock_irqrestore(&qe_gc->lock, flags); } +static void qe_gpio_set_multiple(struct gpio_chip *gc, + unsigned long *mask, unsigned long *bits) +{ + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc); + struct qe_pio_regs __iomem *regs = mm_gc->regs; + unsigned long flags; + int i; + + spin_lock_irqsave(&qe_gc->lock, flags); + + for (i = 0; i < gc->ngpio; i++) { + if (*mask == 0) + break; + if (__test_and_clear_bit(i, mask)) { + if (test_bit(i, bits)) + qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i)); + else + qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i)); + } + } + + out_be32(®s->cpdata, qe_gc->cpdata); + + spin_unlock_irqrestore(&qe_gc->lock, flags); +} + static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) { struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); @@ -298,6 +325,7 @@ static int __init qe_add_gpiochips(void) gc->direction_output = qe_gpio_dir_out; gc->get = qe_gpio_get; gc->set = qe_gpio_set; + gc->set_multiple = qe_gpio_set_multiple; ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc); if (ret)