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cxl: Dump PSL_FIR1/2 registers on PSL9 error irq

Message ID 20170907121346.22011-1-vaibhav@linux.vnet.ibm.com (mailing list archive)
State Changes Requested
Headers show
Series cxl: Dump PSL_FIR1/2 registers on PSL9 error irq | expand

Commit Message

Vaibhav Jain Sept. 7, 2017, 12:13 p.m. UTC
For PSL9 currently we aren't dumping the PSL FIR1/2 registers when a
PSL error interrupt is triggered. Contents of these registers are
useful in debugging AFU issues.

This patch fixes issue by updating the cxl_native_err_irq_dump_regs()
to dump these regs on PSL error interrupt thereby bringing the
behavior in line with PSL on POWER-8.

Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
---
 drivers/misc/cxl/native.c | 13 +++++++++++--
 drivers/misc/cxl/pci.c    |  1 +
 2 files changed, 12 insertions(+), 2 deletions(-)

Comments

Christophe Lombard Sept. 7, 2017, 5:25 p.m. UTC | #1
Le 07/09/2017 à 14:13, Vaibhav Jain a écrit :
> For PSL9 currently we aren't dumping the PSL FIR1/2 registers when a
> PSL error interrupt is triggered. Contents of these registers are
> useful in debugging AFU issues.
>
> This patch fixes issue by updating the cxl_native_err_irq_dump_regs()
> to dump these regs on PSL error interrupt thereby bringing the
> behavior in line with PSL on POWER-8.
>
> Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
> ---
>   drivers/misc/cxl/native.c | 13 +++++++++++--
>   drivers/misc/cxl/pci.c    |  1 +
>   2 files changed, 12 insertions(+), 2 deletions(-)

sounds good.

Acked-by:  Christophe Lombard <clombard@linux.vnet.ibm.com>
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    <div class="moz-cite-prefix">Le 07/09/2017 à 14:13, Vaibhav Jain a
      écrit :<br>
    </div>
    <blockquote type="cite"
      cite="mid:20170907121346.22011-1-vaibhav@linux.vnet.ibm.com">
      <pre wrap="">For PSL9 currently we aren't dumping the PSL FIR1/2 registers when a
PSL error interrupt is triggered. Contents of these registers are
useful in debugging AFU issues.

This patch fixes issue by updating the cxl_native_err_irq_dump_regs()
to dump these regs on PSL error interrupt thereby bringing the
behavior in line with PSL on POWER-8.

Signed-off-by: Vaibhav Jain <a class="moz-txt-link-rfc2396E" href="mailto:vaibhav@linux.vnet.ibm.com">&lt;vaibhav@linux.vnet.ibm.com&gt;</a>
---
 drivers/misc/cxl/native.c | 13 +++++++++++--
 drivers/misc/cxl/pci.c    |  1 +
 2 files changed, 12 insertions(+), 2 deletions(-)
</pre>
    </blockquote>
    <br>
    sounds good.<br>
    <br>
    Acked-by:  Christophe Lombard <a class="moz-txt-link-rfc2396E"
      href="mailto:clombard@linux.vnet.ibm.com">&lt;clombard@linux.vnet.ibm.com&gt;</a><br>
    <br>
  </body>
</html>
Andrew Donnellan Sept. 8, 2017, 1:15 a.m. UTC | #2
LGTM

Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>

On 07/09/17 22:13, Vaibhav Jain wrote:
> For PSL9 currently we aren't dumping the PSL FIR1/2 registers when a
> PSL error interrupt is triggered. Contents of these registers are
> useful in debugging AFU issues.
> 
> This patch fixes issue by updating the cxl_native_err_irq_dump_regs()
> to dump these regs on PSL error interrupt thereby bringing the
> behavior in line with PSL on POWER-8.
> 
> Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
> ---
>   drivers/misc/cxl/native.c | 13 +++++++++++--
>   drivers/misc/cxl/pci.c    |  1 +
>   2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c
> index 4a82c313cf71..60b91e95821d 100644
> --- a/drivers/misc/cxl/native.c
> +++ b/drivers/misc/cxl/native.c
> @@ -1261,8 +1261,17 @@ void cxl_native_err_irq_dump_regs(struct cxl *adapter)
>   {
>   	u64 fir1, fir2;
>   
> -	fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
> -	fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
> +	if (cxl_is_power8()) {
> +		fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
> +		fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
> +	} else if (cxl_is_power9()) {
> +		fir1 = cxl_p1_read(adapter, CXL_PSL9_FIR1);
> +		fir2 = cxl_p1_read(adapter, CXL_PSL9_FIR2);
> +	} else {
> +		/* Dont report garbage */
> +		fir1 = fir2 = 0;
> +		WARN_ON(1);
> +	}
>   
>   	dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2);
>   }
> diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
> index d18b3d9292fd..597e145f38e3 100644
> --- a/drivers/misc/cxl/pci.c
> +++ b/drivers/misc/cxl/pci.c
> @@ -1762,6 +1762,7 @@ static const struct cxl_service_layer_ops psl9_ops = {
>   	.debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
>   	.debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
>   	.psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
> +	.err_irq_dump_registers = cxl_native_err_irq_dump_regs,
>   	.debugfs_stop_trace = cxl_stop_trace_psl9,
>   	.write_timebase_ctrl = write_timebase_ctrl_psl9,
>   	.timebase_read = timebase_read_psl9,
>
Vaibhav Jain Oct. 9, 2017, 4:46 p.m. UTC | #3
Fred just pointed out that there is no register named FIR2 on PSL9
instead we have a FIR_MASK register in its place. So I will re-spin this
patch with the correct register name.

Thanks everyone for the review and to Fred for pointing out the issue.
diff mbox series

Patch

diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c
index 4a82c313cf71..60b91e95821d 100644
--- a/drivers/misc/cxl/native.c
+++ b/drivers/misc/cxl/native.c
@@ -1261,8 +1261,17 @@  void cxl_native_err_irq_dump_regs(struct cxl *adapter)
 {
 	u64 fir1, fir2;
 
-	fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
-	fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
+	if (cxl_is_power8()) {
+		fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1);
+		fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2);
+	} else if (cxl_is_power9()) {
+		fir1 = cxl_p1_read(adapter, CXL_PSL9_FIR1);
+		fir2 = cxl_p1_read(adapter, CXL_PSL9_FIR2);
+	} else {
+		/* Dont report garbage */
+		fir1 = fir2 = 0;
+		WARN_ON(1);
+	}
 
 	dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2);
 }
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index d18b3d9292fd..597e145f38e3 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -1762,6 +1762,7 @@  static const struct cxl_service_layer_ops psl9_ops = {
 	.debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
 	.debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
 	.psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
+	.err_irq_dump_registers = cxl_native_err_irq_dump_regs,
 	.debugfs_stop_trace = cxl_stop_trace_psl9,
 	.write_timebase_ctrl = write_timebase_ctrl_psl9,
 	.timebase_read = timebase_read_psl9,