From patchwork Fri May 25 21:48:45 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Al Viro X-Patchwork-Id: 161429 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 1481EB6F13 for ; Sat, 26 May 2012 07:50:26 +1000 (EST) Received: from ZenIV.linux.org.uk (zeniv.linux.org.uk [195.92.253.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 486ECB6EF1 for ; Sat, 26 May 2012 07:49:00 +1000 (EST) Received: from viro by ZenIV.linux.org.uk with local (Exim 4.76 #1 (Red Hat Linux)) id 1SY2NJ-0006jr-RL; Fri, 25 May 2012 21:48:45 +0000 Date: Fri, 25 May 2012 22:48:45 +0100 From: Al Viro To: Stephen Rothwell Subject: Re: [git pull] signals, the first series Message-ID: <20120525214845.GQ11775@ZenIV.linux.org.uk> References: <20120522043525.GI11775@ZenIV.linux.org.uk> <20120522180635.93ba83a63481b2364bd8f425@canb.auug.org.au> <20120523151405.f264a88ca4edf8d22c08c86c@canb.auug.org.au> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20120523151405.f264a88ca4edf8d22c08c86c@canb.auug.org.au> User-Agent: Mutt/1.5.21 (2010-09-15) Cc: linux-arch@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, Andrew Morton , Linus Torvalds , linux-kernel@vger.kernel.org X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org On Wed, May 23, 2012 at 03:14:05PM +1000, Stephen Rothwell wrote: > OK, it seem that most of this has been in Andrew's tree for a while, > sorry about that. Grr... *Another* missing prereq for task_work_add() series, this time on ppc64. Could somebody familiar with that beast take a look at this and tell if the change is sane? What we want is r0 = r3 & MSR_PR ? _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME | _TIF_SIGPENDING : _TIF_NEED_RESCHED; and when Roland re-added NOTIFY_RESUME he'd missed that hack (non-PREEMPT variant and 32bit code all just check _TIF_USER_WORK_MASK, so updating it had been enough in those cases). I don't have the hardware in question; the same instructions in userland on ppc32 box produce the right value. Unless NAKed I'm going to throw that one into the second pull request from signal.git, so if anyone has objections, please yell. I'll gladly replace that with better solution if one shows up (or, better yet, goes via ppc tree). AFAICS the diff below should work, but whether it's the best variant or not... No idea. Back to massaging VFS queue for pull... diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index ed1718f..e4fd9bb 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -563,9 +563,10 @@ _GLOBAL(ret_from_except_lite) li r0,_TIF_NEED_RESCHED /* bits to check */ ld r3,_MSR(r1) ld r4,TI_FLAGS(r9) - /* Move MSR_PR bit in r3 to _TIF_SIGPENDING position in r0 */ + /* Add MSR_PR bit in r3 in _TIF_SIGPENDING and _TIF_NOTIFY_RESUME positions in r0 */ rlwimi r0,r3,32+TIF_SIGPENDING-MSR_PR_LG,_TIF_SIGPENDING - and. r0,r4,r0 /* check NEED_RESCHED and maybe SIGPENDING */ + rlwimi r0,r3,32+TIF_NOTIFY_RESUME-MSR_PR_LG,_TIF_NOTIFY_RESUME + and. r0,r4,r0 /* check NEED_RESCHED and maybe SIGPENDING/NOTIFY_RESUME */ bne do_work #else /* !CONFIG_PREEMPT */