From patchwork Mon Jul 13 15:19:44 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Vorontsov X-Patchwork-Id: 29738 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@bilbo.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id 03782B7085 for ; Tue, 14 Jul 2009 01:22:30 +1000 (EST) Received: by ozlabs.org (Postfix) id EA67FDDDE6; Tue, 14 Jul 2009 01:22:29 +1000 (EST) Delivered-To: patchwork-incoming@ozlabs.org Received: from bilbo.ozlabs.org (bilbo.ozlabs.org [203.10.76.25]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "bilbo.ozlabs.org", Issuer "CAcert Class 3 Root" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id E7D52DDDA2 for ; Tue, 14 Jul 2009 01:22:29 +1000 (EST) Received: from bilbo.ozlabs.org (localhost [127.0.0.1]) by bilbo.ozlabs.org (Postfix) with ESMTP id 1BCA9B78FB for ; Tue, 14 Jul 2009 01:20:07 +1000 (EST) Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id B3AC3B721B for ; Tue, 14 Jul 2009 01:19:46 +1000 (EST) Received: by ozlabs.org (Postfix) id 9FF53DDDE9; Tue, 14 Jul 2009 01:19:46 +1000 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: from buildserver.ru.mvista.com (unknown [213.79.90.228]) by ozlabs.org (Postfix) with ESMTP id C9953DDDD4 for ; Tue, 14 Jul 2009 01:19:45 +1000 (EST) Received: from localhost (unknown [10.150.0.9]) by buildserver.ru.mvista.com (Postfix) with ESMTP id 5CC918826; Mon, 13 Jul 2009 20:19:44 +0500 (SAMST) Date: Mon, 13 Jul 2009 19:19:44 +0400 From: Anton Vorontsov To: David Brownell Subject: [PATCH 2/2] powerpc/qe: Implement set_sync() callback for QE GPIOs Message-ID: <20090713151944.GB4486@oksana.dev.rtsoft.ru> References: <20090713151911.GA28114@oksana.dev.rtsoft.ru> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20090713151911.GA28114@oksana.dev.rtsoft.ru> User-Agent: Mutt/1.5.20 (2009-06-14) Cc: linuxppc-dev@ozlabs.org, linux-kernel@vger.kernel.org X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org This is needed to set GPIO's values synchronously. Signed-off-by: Anton Vorontsov --- arch/powerpc/include/asm/gpio.h | 11 +++++++++++ arch/powerpc/sysdev/qe_lib/gpio.c | 27 +++++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/include/asm/gpio.h b/arch/powerpc/include/asm/gpio.h index ea04632..899f365 100644 --- a/arch/powerpc/include/asm/gpio.h +++ b/arch/powerpc/include/asm/gpio.h @@ -33,6 +33,17 @@ static inline void gpio_set_value(unsigned int gpio, int value) __gpio_set_value(gpio, value); } +static inline int gpio_can_set_values_sync(unsigned num, unsigned *gpios) +{ + return __gpio_can_set_values_sync(num, gpios); +} + +static inline void gpio_set_values_sync(unsigned num, unsigned *gpios, + int *values) +{ + __gpio_set_values_sync(num, gpios, values); +} + static inline int gpio_cansleep(unsigned int gpio) { return __gpio_cansleep(gpio); diff --git a/arch/powerpc/sysdev/qe_lib/gpio.c b/arch/powerpc/sysdev/qe_lib/gpio.c index 3485288..6cfe784 100644 --- a/arch/powerpc/sysdev/qe_lib/gpio.c +++ b/arch/powerpc/sysdev/qe_lib/gpio.c @@ -84,6 +84,32 @@ static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) spin_unlock_irqrestore(&qe_gc->lock, flags); } +static void qe_gpio_set_sync(struct gpio_chip *gc, unsigned int num, + unsigned int *gpios, int *vals) +{ + struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); + struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc); + struct qe_pio_regs __iomem *regs = mm_gc->regs; + unsigned long flags; + int i; + + spin_lock_irqsave(&qe_gc->lock, flags); + + for (i = 0; i < num; i++) { + unsigned int gpio = gpios[i] - gc->base; + u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); + + if (vals[i]) + qe_gc->cpdata |= pin_mask; + else + qe_gc->cpdata &= ~pin_mask; + } + + out_be32(®s->cpdata, qe_gc->cpdata); + + spin_unlock_irqrestore(&qe_gc->lock, flags); +} + static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) { struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); @@ -328,6 +354,7 @@ static int __init qe_add_gpiochips(void) gc->direction_output = qe_gpio_dir_out; gc->get = qe_gpio_get; gc->set = qe_gpio_set; + gc->set_sync = qe_gpio_set_sync; ret = of_mm_gpiochip_add(np, mm_gc); if (ret)