| Message ID | 1612335337-1888-4-git-send-email-atrajeev@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | powerpc/perf: Add Performance Monitor Counters to extended regs | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch powerpc/merge (44158b256b30415079588d0fcb1bccbdc2ccd009) |
| snowpatch_ozlabs/build-ppc64le | success | Build succeeded |
| snowpatch_ozlabs/build-ppc64be | success | Build succeeded |
| snowpatch_ozlabs/build-ppc64e | success | Build succeeded |
| snowpatch_ozlabs/build-pmac32 | success | Build succeeded |
| snowpatch_ozlabs/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 63 lines checked |
| snowpatch_ozlabs/needsstable | success | Patch has no Fixes tags |
Em Wed, Feb 03, 2021 at 01:55:37AM -0500, Athira Rajeev escreveu: > To enable presenting of Performance Monitor Counter Registers > (PMC1 to PMC6) as part of extended regsiters, patch adds these > to sample_reg_mask in the tool side (to use with -I? option). > > Simplified the PERF_REG_PMU_MASK_300/31 definition. Excluded the > unsupported SPRs (MMCR3, SIER2, SIER3) from extended mask value for > CPU_FTR_ARCH_300. Applied just 3/3, the tooling part, to my local branch, please holler if I should wait a bit more. - Arnaldo > Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> > --- > tools/arch/powerpc/include/uapi/asm/perf_regs.h | 28 +++++++++++++++++++------ > tools/perf/arch/powerpc/include/perf_regs.h | 6 ++++++ > tools/perf/arch/powerpc/util/perf_regs.c | 6 ++++++ > 3 files changed, 34 insertions(+), 6 deletions(-) > > diff --git a/tools/arch/powerpc/include/uapi/asm/perf_regs.h b/tools/arch/powerpc/include/uapi/asm/perf_regs.h > index bdf5f10f8b9f..578b3ee86105 100644 > --- a/tools/arch/powerpc/include/uapi/asm/perf_regs.h > +++ b/tools/arch/powerpc/include/uapi/asm/perf_regs.h > @@ -55,17 +55,33 @@ enum perf_event_powerpc_regs { > PERF_REG_POWERPC_MMCR3, > PERF_REG_POWERPC_SIER2, > PERF_REG_POWERPC_SIER3, > + PERF_REG_POWERPC_PMC1, > + PERF_REG_POWERPC_PMC2, > + PERF_REG_POWERPC_PMC3, > + PERF_REG_POWERPC_PMC4, > + PERF_REG_POWERPC_PMC5, > + PERF_REG_POWERPC_PMC6, > /* Max regs without the extended regs */ > PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1, > }; > > #define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1) > > -/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 */ > -#define PERF_REG_PMU_MASK_300 (((1ULL << (PERF_REG_POWERPC_MMCR2 + 1)) - 1) - PERF_REG_PMU_MASK) > -/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31 */ > -#define PERF_REG_PMU_MASK_31 (((1ULL << (PERF_REG_POWERPC_SIER3 + 1)) - 1) - PERF_REG_PMU_MASK) > +/* Exclude MMCR3, SIER2, SIER3 for CPU_FTR_ARCH_300 */ > +#define PERF_EXCLUDE_REG_EXT_300 (7ULL << PERF_REG_POWERPC_MMCR3) > > -#define PERF_REG_MAX_ISA_300 (PERF_REG_POWERPC_MMCR2 + 1) > -#define PERF_REG_MAX_ISA_31 (PERF_REG_POWERPC_SIER3 + 1) > +/* > + * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 > + * includes 9 SPRS from MMCR0 to PMC6 excluding the > + * unsupported SPRS in PERF_EXCLUDE_REG_EXT_300. > + */ > +#define PERF_REG_PMU_MASK_300 ((0xfffULL << PERF_REG_POWERPC_MMCR0) - PERF_EXCLUDE_REG_EXT_300) > + > +/* > + * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31 > + * includes 12 SPRs from MMCR0 to PMC6. > + */ > +#define PERF_REG_PMU_MASK_31 (0xfffULL << PERF_REG_POWERPC_MMCR0) > + > +#define PERF_REG_EXTENDED_MAX (PERF_REG_POWERPC_PMC6 + 1) > #endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */ > diff --git a/tools/perf/arch/powerpc/include/perf_regs.h b/tools/perf/arch/powerpc/include/perf_regs.h > index 63f3ac91049f..98b6f9eabfc3 100644 > --- a/tools/perf/arch/powerpc/include/perf_regs.h > +++ b/tools/perf/arch/powerpc/include/perf_regs.h > @@ -71,6 +71,12 @@ > [PERF_REG_POWERPC_MMCR3] = "mmcr3", > [PERF_REG_POWERPC_SIER2] = "sier2", > [PERF_REG_POWERPC_SIER3] = "sier3", > + [PERF_REG_POWERPC_PMC1] = "pmc1", > + [PERF_REG_POWERPC_PMC2] = "pmc2", > + [PERF_REG_POWERPC_PMC3] = "pmc3", > + [PERF_REG_POWERPC_PMC4] = "pmc4", > + [PERF_REG_POWERPC_PMC5] = "pmc5", > + [PERF_REG_POWERPC_PMC6] = "pmc6", > }; > > static inline const char *perf_reg_name(int id) > diff --git a/tools/perf/arch/powerpc/util/perf_regs.c b/tools/perf/arch/powerpc/util/perf_regs.c > index 2b6d4704e3aa..8116a253f91f 100644 > --- a/tools/perf/arch/powerpc/util/perf_regs.c > +++ b/tools/perf/arch/powerpc/util/perf_regs.c > @@ -68,6 +68,12 @@ > SMPL_REG(mmcr3, PERF_REG_POWERPC_MMCR3), > SMPL_REG(sier2, PERF_REG_POWERPC_SIER2), > SMPL_REG(sier3, PERF_REG_POWERPC_SIER3), > + SMPL_REG(pmc1, PERF_REG_POWERPC_PMC1), > + SMPL_REG(pmc2, PERF_REG_POWERPC_PMC2), > + SMPL_REG(pmc3, PERF_REG_POWERPC_PMC3), > + SMPL_REG(pmc4, PERF_REG_POWERPC_PMC4), > + SMPL_REG(pmc5, PERF_REG_POWERPC_PMC5), > + SMPL_REG(pmc6, PERF_REG_POWERPC_PMC6), > SMPL_REG_END > }; > > -- > 1.8.3.1 >
> On 03-Feb-2021, at 9:55 PM, Arnaldo Carvalho de Melo <acme@kernel.org> wrote: > > Em Wed, Feb 03, 2021 at 01:55:37AM -0500, Athira Rajeev escreveu: >> To enable presenting of Performance Monitor Counter Registers >> (PMC1 to PMC6) as part of extended regsiters, patch adds these >> to sample_reg_mask in the tool side (to use with -I? option). >> >> Simplified the PERF_REG_PMU_MASK_300/31 definition. Excluded the >> unsupported SPRs (MMCR3, SIER2, SIER3) from extended mask value for >> CPU_FTR_ARCH_300. > > Applied just 3/3, the tooling part, to my local branch, please holler if > I should wait a bit more. > > - Arnaldo > Thanks Arnaldo for taking the tool side changes. Athira. >> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> >> --- >> tools/arch/powerpc/include/uapi/asm/perf_regs.h | 28 +++++++++++++++++++------ >> tools/perf/arch/powerpc/include/perf_regs.h | 6 ++++++ >> tools/perf/arch/powerpc/util/perf_regs.c | 6 ++++++ >> 3 files changed, 34 insertions(+), 6 deletions(-) >> >> diff --git a/tools/arch/powerpc/include/uapi/asm/perf_regs.h b/tools/arch/powerpc/include/uapi/asm/perf_regs.h >> index bdf5f10f8b9f..578b3ee86105 100644 >> --- a/tools/arch/powerpc/include/uapi/asm/perf_regs.h >> +++ b/tools/arch/powerpc/include/uapi/asm/perf_regs.h >> @@ -55,17 +55,33 @@ enum perf_event_powerpc_regs { >> PERF_REG_POWERPC_MMCR3, >> PERF_REG_POWERPC_SIER2, >> PERF_REG_POWERPC_SIER3, >> + PERF_REG_POWERPC_PMC1, >> + PERF_REG_POWERPC_PMC2, >> + PERF_REG_POWERPC_PMC3, >> + PERF_REG_POWERPC_PMC4, >> + PERF_REG_POWERPC_PMC5, >> + PERF_REG_POWERPC_PMC6, >> /* Max regs without the extended regs */ >> PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1, >> }; >> >> #define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1) >> >> -/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 */ >> -#define PERF_REG_PMU_MASK_300 (((1ULL << (PERF_REG_POWERPC_MMCR2 + 1)) - 1) - PERF_REG_PMU_MASK) >> -/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31 */ >> -#define PERF_REG_PMU_MASK_31 (((1ULL << (PERF_REG_POWERPC_SIER3 + 1)) - 1) - PERF_REG_PMU_MASK) >> +/* Exclude MMCR3, SIER2, SIER3 for CPU_FTR_ARCH_300 */ >> +#define PERF_EXCLUDE_REG_EXT_300 (7ULL << PERF_REG_POWERPC_MMCR3) >> >> -#define PERF_REG_MAX_ISA_300 (PERF_REG_POWERPC_MMCR2 + 1) >> -#define PERF_REG_MAX_ISA_31 (PERF_REG_POWERPC_SIER3 + 1) >> +/* >> + * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 >> + * includes 9 SPRS from MMCR0 to PMC6 excluding the >> + * unsupported SPRS in PERF_EXCLUDE_REG_EXT_300. >> + */ >> +#define PERF_REG_PMU_MASK_300 ((0xfffULL << PERF_REG_POWERPC_MMCR0) - PERF_EXCLUDE_REG_EXT_300) >> + >> +/* >> + * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31 >> + * includes 12 SPRs from MMCR0 to PMC6. >> + */ >> +#define PERF_REG_PMU_MASK_31 (0xfffULL << PERF_REG_POWERPC_MMCR0) >> + >> +#define PERF_REG_EXTENDED_MAX (PERF_REG_POWERPC_PMC6 + 1) >> #endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */ >> diff --git a/tools/perf/arch/powerpc/include/perf_regs.h b/tools/perf/arch/powerpc/include/perf_regs.h >> index 63f3ac91049f..98b6f9eabfc3 100644 >> --- a/tools/perf/arch/powerpc/include/perf_regs.h >> +++ b/tools/perf/arch/powerpc/include/perf_regs.h >> @@ -71,6 +71,12 @@ >> [PERF_REG_POWERPC_MMCR3] = "mmcr3", >> [PERF_REG_POWERPC_SIER2] = "sier2", >> [PERF_REG_POWERPC_SIER3] = "sier3", >> + [PERF_REG_POWERPC_PMC1] = "pmc1", >> + [PERF_REG_POWERPC_PMC2] = "pmc2", >> + [PERF_REG_POWERPC_PMC3] = "pmc3", >> + [PERF_REG_POWERPC_PMC4] = "pmc4", >> + [PERF_REG_POWERPC_PMC5] = "pmc5", >> + [PERF_REG_POWERPC_PMC6] = "pmc6", >> }; >> >> static inline const char *perf_reg_name(int id) >> diff --git a/tools/perf/arch/powerpc/util/perf_regs.c b/tools/perf/arch/powerpc/util/perf_regs.c >> index 2b6d4704e3aa..8116a253f91f 100644 >> --- a/tools/perf/arch/powerpc/util/perf_regs.c >> +++ b/tools/perf/arch/powerpc/util/perf_regs.c >> @@ -68,6 +68,12 @@ >> SMPL_REG(mmcr3, PERF_REG_POWERPC_MMCR3), >> SMPL_REG(sier2, PERF_REG_POWERPC_SIER2), >> SMPL_REG(sier3, PERF_REG_POWERPC_SIER3), >> + SMPL_REG(pmc1, PERF_REG_POWERPC_PMC1), >> + SMPL_REG(pmc2, PERF_REG_POWERPC_PMC2), >> + SMPL_REG(pmc3, PERF_REG_POWERPC_PMC3), >> + SMPL_REG(pmc4, PERF_REG_POWERPC_PMC4), >> + SMPL_REG(pmc5, PERF_REG_POWERPC_PMC5), >> + SMPL_REG(pmc6, PERF_REG_POWERPC_PMC6), >> SMPL_REG_END >> }; >> >> -- >> 1.8.3.1 >> > > -- > > - Arnaldo
diff --git a/tools/arch/powerpc/include/uapi/asm/perf_regs.h b/tools/arch/powerpc/include/uapi/asm/perf_regs.h index bdf5f10f8b9f..578b3ee86105 100644 --- a/tools/arch/powerpc/include/uapi/asm/perf_regs.h +++ b/tools/arch/powerpc/include/uapi/asm/perf_regs.h @@ -55,17 +55,33 @@ enum perf_event_powerpc_regs { PERF_REG_POWERPC_MMCR3, PERF_REG_POWERPC_SIER2, PERF_REG_POWERPC_SIER3, + PERF_REG_POWERPC_PMC1, + PERF_REG_POWERPC_PMC2, + PERF_REG_POWERPC_PMC3, + PERF_REG_POWERPC_PMC4, + PERF_REG_POWERPC_PMC5, + PERF_REG_POWERPC_PMC6, /* Max regs without the extended regs */ PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1, }; #define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1) -/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 */ -#define PERF_REG_PMU_MASK_300 (((1ULL << (PERF_REG_POWERPC_MMCR2 + 1)) - 1) - PERF_REG_PMU_MASK) -/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31 */ -#define PERF_REG_PMU_MASK_31 (((1ULL << (PERF_REG_POWERPC_SIER3 + 1)) - 1) - PERF_REG_PMU_MASK) +/* Exclude MMCR3, SIER2, SIER3 for CPU_FTR_ARCH_300 */ +#define PERF_EXCLUDE_REG_EXT_300 (7ULL << PERF_REG_POWERPC_MMCR3) -#define PERF_REG_MAX_ISA_300 (PERF_REG_POWERPC_MMCR2 + 1) -#define PERF_REG_MAX_ISA_31 (PERF_REG_POWERPC_SIER3 + 1) +/* + * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 + * includes 9 SPRS from MMCR0 to PMC6 excluding the + * unsupported SPRS in PERF_EXCLUDE_REG_EXT_300. + */ +#define PERF_REG_PMU_MASK_300 ((0xfffULL << PERF_REG_POWERPC_MMCR0) - PERF_EXCLUDE_REG_EXT_300) + +/* + * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31 + * includes 12 SPRs from MMCR0 to PMC6. + */ +#define PERF_REG_PMU_MASK_31 (0xfffULL << PERF_REG_POWERPC_MMCR0) + +#define PERF_REG_EXTENDED_MAX (PERF_REG_POWERPC_PMC6 + 1) #endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */ diff --git a/tools/perf/arch/powerpc/include/perf_regs.h b/tools/perf/arch/powerpc/include/perf_regs.h index 63f3ac91049f..98b6f9eabfc3 100644 --- a/tools/perf/arch/powerpc/include/perf_regs.h +++ b/tools/perf/arch/powerpc/include/perf_regs.h @@ -71,6 +71,12 @@ [PERF_REG_POWERPC_MMCR3] = "mmcr3", [PERF_REG_POWERPC_SIER2] = "sier2", [PERF_REG_POWERPC_SIER3] = "sier3", + [PERF_REG_POWERPC_PMC1] = "pmc1", + [PERF_REG_POWERPC_PMC2] = "pmc2", + [PERF_REG_POWERPC_PMC3] = "pmc3", + [PERF_REG_POWERPC_PMC4] = "pmc4", + [PERF_REG_POWERPC_PMC5] = "pmc5", + [PERF_REG_POWERPC_PMC6] = "pmc6", }; static inline const char *perf_reg_name(int id) diff --git a/tools/perf/arch/powerpc/util/perf_regs.c b/tools/perf/arch/powerpc/util/perf_regs.c index 2b6d4704e3aa..8116a253f91f 100644 --- a/tools/perf/arch/powerpc/util/perf_regs.c +++ b/tools/perf/arch/powerpc/util/perf_regs.c @@ -68,6 +68,12 @@ SMPL_REG(mmcr3, PERF_REG_POWERPC_MMCR3), SMPL_REG(sier2, PERF_REG_POWERPC_SIER2), SMPL_REG(sier3, PERF_REG_POWERPC_SIER3), + SMPL_REG(pmc1, PERF_REG_POWERPC_PMC1), + SMPL_REG(pmc2, PERF_REG_POWERPC_PMC2), + SMPL_REG(pmc3, PERF_REG_POWERPC_PMC3), + SMPL_REG(pmc4, PERF_REG_POWERPC_PMC4), + SMPL_REG(pmc5, PERF_REG_POWERPC_PMC5), + SMPL_REG(pmc6, PERF_REG_POWERPC_PMC6), SMPL_REG_END };
To enable presenting of Performance Monitor Counter Registers (PMC1 to PMC6) as part of extended regsiters, patch adds these to sample_reg_mask in the tool side (to use with -I? option). Simplified the PERF_REG_PMU_MASK_300/31 definition. Excluded the unsupported SPRs (MMCR3, SIER2, SIER3) from extended mask value for CPU_FTR_ARCH_300. Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> --- tools/arch/powerpc/include/uapi/asm/perf_regs.h | 28 +++++++++++++++++++------ tools/perf/arch/powerpc/include/perf_regs.h | 6 ++++++ tools/perf/arch/powerpc/util/perf_regs.c | 6 ++++++ 3 files changed, 34 insertions(+), 6 deletions(-)