| Message ID | 1598424029-1662-1-git-send-email-atrajeev@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 82715a0f332843d3a1830d7ebc9ac7c99a00c880 |
| Headers | show |
| Series | powerpc/perf: Fix reading of MSR[HV PR] bits in trace-imc | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch powerpc/merge (d4ecce4dcc8f8820286cf4e0859850c555e89854) |
| snowpatch_ozlabs/build-ppc64le | warning | Upstream build failed, couldn't test patch |
| snowpatch_ozlabs/build-ppc64be | warning | Upstream build failed, couldn't test patch |
| snowpatch_ozlabs/build-ppc64e | warning | Upstream build failed, couldn't test patch |
| snowpatch_ozlabs/build-pmac32 | warning | Upstream build failed, couldn't test patch |
| snowpatch_ozlabs/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 16 lines checked |
| snowpatch_ozlabs/needsstable | success | Patch fixes a commit that hasn't been released yet |
On Wed, 26 Aug 2020 02:40:29 -0400, Athira Rajeev wrote: > IMC trace-mode uses MSR[HV PR] bits to set the cpumode > for the instruction pointer captured in each sample. > The bits are fetched from third DW of the trace record. > Reading third DW from IMC trace record should use be64_to_cpu > along with READ_ONCE inorder to fetch correct MSR[HV PR] bits. > Patch addresses this change. > > [...] Applied to powerpc/fixes. [1/1] powerpc/perf: Fix reading of MSR[HV/PR] bits in trace-imc https://git.kernel.org/powerpc/c/82715a0f332843d3a1830d7ebc9ac7c99a00c880 cheers
diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c index a45d694..62d0b54 100644 --- a/arch/powerpc/perf/imc-pmu.c +++ b/arch/powerpc/perf/imc-pmu.c @@ -1289,7 +1289,7 @@ static int trace_imc_prepare_sample(struct trace_imc_data *mem, header->misc = 0; if (cpu_has_feature(CPU_FTR_ARCH_31)) { - switch (IMC_TRACE_RECORD_VAL_HVPR(mem->val)) { + switch (IMC_TRACE_RECORD_VAL_HVPR(be64_to_cpu(READ_ONCE(mem->val)))) { case 0:/* when MSR HV and PR not set in the trace-record */ header->misc |= PERF_RECORD_MISC_GUEST_KERNEL; break; @@ -1297,7 +1297,7 @@ static int trace_imc_prepare_sample(struct trace_imc_data *mem, header->misc |= PERF_RECORD_MISC_GUEST_USER; break; case 2: /* MSR HV is 1 and PR is 0 */ - header->misc |= PERF_RECORD_MISC_HYPERVISOR; + header->misc |= PERF_RECORD_MISC_KERNEL; break; case 3: /* MSR HV is 1 and PR is 1 */ header->misc |= PERF_RECORD_MISC_USER;
IMC trace-mode uses MSR[HV PR] bits to set the cpumode for the instruction pointer captured in each sample. The bits are fetched from third DW of the trace record. Reading third DW from IMC trace record should use be64_to_cpu along with READ_ONCE inorder to fetch correct MSR[HV PR] bits. Patch addresses this change. Currently we are using `PERF_RECORD_MISC_HYPERVISOR` as cpumode if MSR HV is 1 and PR is 0 which means the address is from host counter. But using `PERF_RECORD_MISC_HYPERVISOR` for host counter data will fail to resolve the `address -> symbol` during `perf report` because perf tools side uses `PERF_RECORD_MISC_KERNEL` to represent the host counter data. Therefore, fix the trace imc sample data to use `PERF_RECORD_MISC_KERNEL` as cpumode for host kernel information. Fixes: 77ca3951cc37 ("powerpc/perf: Add kernel support for new MSR[HV PR] bits in trace-imc") Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> --- arch/powerpc/perf/imc-pmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)