| Message ID | 1596699585-27429-1-git-send-email-shengjiu.wang@nxp.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | ASoC: fsl-asoc-card: Get "extal" clock rate by clk_get_rate | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch powerpc/merge (3cd2184115b85cc8242fec3d42529cd112962984) |
| snowpatch_ozlabs/build-ppc64le | warning | Upstream build failed, couldn't test patch |
| snowpatch_ozlabs/build-ppc64be | warning | Upstream build failed, couldn't test patch |
| snowpatch_ozlabs/build-ppc64e | warning | Upstream build failed, couldn't test patch |
| snowpatch_ozlabs/build-pmac32 | warning | Upstream build failed, couldn't test patch |
| snowpatch_ozlabs/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 13 lines checked |
| snowpatch_ozlabs/needsstable | success | Patch has no Fixes tags |
On Thu, Aug 06, 2020 at 03:39:45PM +0800, Shengjiu Wang wrote: > } else if (of_node_name_eq(cpu_np, "esai")) { > + struct clk *esai_clk = clk_get(&cpu_pdev->dev, "extal"); > + > + if (!IS_ERR(esai_clk)) { > + priv->cpu_priv.sysclk_freq[TX] = clk_get_rate(esai_clk); > + priv->cpu_priv.sysclk_freq[RX] = clk_get_rate(esai_clk); > + clk_put(esai_clk); > + } This should handle probe deferral. Also if this clock is in use shouldn't we be enabling it? It looks like it's intended to be a crystal so it's probably forced on all the time but sometimes there's power control for crystals, or perhaps someone might do something unusual with the hardware.
On Thu, Aug 6, 2020 at 8:39 PM Mark Brown <broonie@kernel.org> wrote: > > On Thu, Aug 06, 2020 at 03:39:45PM +0800, Shengjiu Wang wrote: > > > } else if (of_node_name_eq(cpu_np, "esai")) { > > + struct clk *esai_clk = clk_get(&cpu_pdev->dev, "extal"); > > + > > + if (!IS_ERR(esai_clk)) { > > + priv->cpu_priv.sysclk_freq[TX] = clk_get_rate(esai_clk); > > + priv->cpu_priv.sysclk_freq[RX] = clk_get_rate(esai_clk); > > + clk_put(esai_clk); > > + } > > This should handle probe deferral. Also if this clock is in use > shouldn't we be enabling it? It looks like it's intended to be a > crystal so it's probably forced on all the time but sometimes there's > power control for crystals, or perhaps someone might do something > unusual with the hardware. Ok, will add handler for probe deferral. This clock is not a crystal, "extal" clock is for cpu dai, it is from soc internal PLL. which is enabled by cpu dai, here is just to get the clock rate. best regards wang shengjiu
diff --git a/sound/soc/fsl/fsl-asoc-card.c b/sound/soc/fsl/fsl-asoc-card.c index 52adedc03245..2c92a5efad61 100644 --- a/sound/soc/fsl/fsl-asoc-card.c +++ b/sound/soc/fsl/fsl-asoc-card.c @@ -696,6 +696,13 @@ static int fsl_asoc_card_probe(struct platform_device *pdev) goto asrc_fail; } } else if (of_node_name_eq(cpu_np, "esai")) { + struct clk *esai_clk = clk_get(&cpu_pdev->dev, "extal"); + + if (!IS_ERR(esai_clk)) { + priv->cpu_priv.sysclk_freq[TX] = clk_get_rate(esai_clk); + priv->cpu_priv.sysclk_freq[RX] = clk_get_rate(esai_clk); + clk_put(esai_clk); + } priv->cpu_priv.sysclk_id[1] = ESAI_HCKT_EXTAL; priv->cpu_priv.sysclk_id[0] = ESAI_HCKR_EXTAL; } else if (of_node_name_eq(cpu_np, "sai")) {
On some platform(.e.g. i.MX8QM MEK), the "extal" clock is different with the mclk of codec, then the clock rate is also different. So it is better to get clock rate of "extal" rate by clk_get_rate, don't reuse the clock rate of mclk. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> --- sound/soc/fsl/fsl-asoc-card.c | 7 +++++++ 1 file changed, 7 insertions(+)