From patchwork Sun Aug 28 21:00:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: maddy X-Patchwork-Id: 663441 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sMnRh0g0Nz9s9c for ; Mon, 29 Aug 2016 07:07:44 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3sMnRg71sDzDrpp for ; Mon, 29 Aug 2016 07:07:43 +1000 (AEST) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3sMnK90kwMzDrh0 for ; Mon, 29 Aug 2016 07:02:04 +1000 (AEST) Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id u7SKx3Sq125698 for ; Sun, 28 Aug 2016 17:02:03 -0400 Received: from e28smtp02.in.ibm.com (e28smtp02.in.ibm.com [125.16.236.2]) by mx0b-001b2d01.pphosted.com with ESMTP id 253r8rpwjg-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Sun, 28 Aug 2016 17:02:02 -0400 Received: from localhost by e28smtp02.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 29 Aug 2016 02:31:57 +0530 X-IBM-Helo: d28dlp02.in.ibm.com X-IBM-MailFrom: maddy@linux.vnet.ibm.com X-IBM-RcptTo: linuxppc-dev@lists.ozlabs.org Received: from d28relay05.in.ibm.com (d28relay05.in.ibm.com [9.184.220.62]) by d28dlp02.in.ibm.com (Postfix) with ESMTP id 6E3F83940060 for ; Mon, 29 Aug 2016 02:31:57 +0530 (IST) Received: from d28av01.in.ibm.com (d28av01.in.ibm.com [9.184.220.63]) by d28relay05.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u7SL1u6t15925316 for ; Mon, 29 Aug 2016 02:31:57 +0530 Received: from d28av01.in.ibm.com (localhost [127.0.0.1]) by d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u7SL1jC5005939 for ; Mon, 29 Aug 2016 02:31:54 +0530 Received: from SrihariSrinidhi.ibm.com ([9.126.239.172]) by d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id u7SL11O8004287; Mon, 29 Aug 2016 02:31:41 +0530 From: Madhavan Srinivasan To: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: [PATCH 06/13] powerpc/perf: Add support for perf_arch_regs in powerpc Date: Mon, 29 Aug 2016 02:30:51 +0530 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1472418058-28659-1-git-send-email-maddy@linux.vnet.ibm.com> References: <1472418058-28659-1-git-send-email-maddy@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16082821-0004-0000-0000-00000305FC24 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16082821-0005-0000-0000-00000EE6576D Message-Id: <1472418058-28659-7-git-send-email-maddy@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-08-28_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1604210000 definitions=main-1608280206 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Madhavan Srinivasan , Russell King , Stephane Eranian , Peter Zijlstra , Catalin Marinas , Will Deacon , Arnaldo Carvalho de Melo , Jiri Olsa , Thomas Gleixner , Sukadev Bhattiprolu , Ingo Molnar Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Patch defines struct perf_arch_regs{} for powerpc and update the per-cpu perf pmu structure to include perf_arch_regs bits. perf_arch_reg_value(), perf_get_arch_reg() and perf_get_arch_regs_mask() are implemented to return proper values for powerpc. Finally adds code to call the processor specific function to update the arch_regs register values. Cc: Thomas Gleixner Cc: Ingo Molnar Cc: Peter Zijlstra Cc: Jiri Olsa Cc: Arnaldo Carvalho de Melo Cc: Stephane Eranian Cc: Russell King Cc: Catalin Marinas Cc: Will Deacon Cc: Benjamin Herrenschmidt Cc: Michael Ellerman Cc: Sukadev Bhattiprolu Signed-off-by: Madhavan Srinivasan --- arch/powerpc/include/asm/perf_event_server.h | 11 ++++++++ arch/powerpc/perf/core-book3s.c | 38 ++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h index e157489ee7a1..65699fefb5a8 100644 --- a/arch/powerpc/include/asm/perf_event_server.h +++ b/arch/powerpc/include/asm/perf_event_server.h @@ -12,6 +12,7 @@ #include #include #include +#include #include /* Update perf_event_print_debug() if this changes */ @@ -21,6 +22,12 @@ struct perf_event; +struct perf_arch_regs { + unsigned long regs[PERF_ARCH_REG_POWERPC_MAX]; +}; + +#define perf_arch_regs perf_arch_regs + /* * This struct provides the constants and functions needed to * describe the PMU on a particular POWER-family CPU. @@ -52,6 +59,10 @@ struct power_pmu { /* BHRB entries in the PMU */ int bhrb_nr; + + /* perf_arch_regs bits */ + u64 ar_mask; + void (*get_arch_regs)(struct perf_arch_regs *regs); }; /* diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 4ed377f0f7b2..6acf086f31b3 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -57,6 +57,9 @@ struct cpu_hw_events { void *bhrb_context; struct perf_branch_stack bhrb_stack; struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; + + /* perf_arch_regs bits */ + struct perf_arch_regs ar_regs; }; static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); @@ -1928,6 +1931,33 @@ ssize_t power_events_sysfs_show(struct device *dev, return sprintf(page, "event=0x%02llx\n", pmu_attr->id); } +u64 perf_get_arch_regs_mask(void) +{ + return ppmu->ar_mask; +} + +struct perf_arch_regs *perf_get_arch_reg() +{ + struct cpu_hw_events *cpuhw; + + cpuhw = this_cpu_ptr(&cpu_hw_events); + if (!ppmu->ar_mask) + return NULL; + + return &cpuhw->ar_regs; +} + +u64 perf_arch_reg_value(struct perf_arch_regs *regs, int idx) +{ + struct cpu_hw_events *cpuhw; + + cpuhw = this_cpu_ptr(&cpu_hw_events); + if (WARN_ON_ONCE(idx >= PERF_ARCH_REG_POWERPC_MAX)) + return 0; + + return cpuhw->ar_regs.regs[idx]; +} + static struct pmu power_pmu = { .pmu_enable = power_pmu_enable, .pmu_disable = power_pmu_disable, @@ -2009,6 +2039,14 @@ static void record_and_restart(struct perf_event *event, unsigned long val, data.br_stack = &cpuhw->bhrb_stack; } + if (event->attr.sample_type & PERF_SAMPLE_REGS_INTR) { + struct cpu_hw_events *cpuhw; + cpuhw = this_cpu_ptr(&cpu_hw_events); + + if (ppmu->get_arch_regs) + ppmu->get_arch_regs(&cpuhw->ar_regs); + } + if (perf_event_overflow(event, &data, regs)) power_pmu_stop(event, 0); }