Message ID | 1457388527-14575-1-git-send-email-oohall@gmail.com (mailing list archive) |
---|---|
State | Accepted |
Headers | show |
On Mon, 2016-07-03 at 22:08:47 UTC, Oliver O'Halloran wrote: > In save_sprs() in process.c contains the following test: > > if (cpu_has_feature(cpu_has_feature(CPU_FTR_ALTIVEC))) > t->vrsave = mfspr(SPRN_VRSAVE); > > CPU feature with the mask 0x1 is CPU_FTR_COHERENT_ICACHE so the test > is equivilent to: > > if (cpu_has_feature(CPU_FTR_ALTIVEC) && > cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) > > On CPUs without support for both (i.e G5) this results in vrsave not being > saved between context switches. The vector register save/restore code > doesn't use VRSAVE to determine which registers to save/restore, > but the value of VRSAVE is used to determine if altivec is being used > in several code paths. > > Signed-off-by: Oliver O'Halloran <oohall@gmail.com> > Signed-off-by: Anton Blanchard <anton@samba.org> > Fixes: 152d523e6307 ("powerpc: Create context switch helpers save_sprs() and restore_sprs()") > Cc: stable@vger.kernel.org Applied to powerpc fixes, thanks. https://git.kernel.org/powerpc/c/01d7c2a2de47890934faba91a7 cheers
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c index dccc87e8fee5..bc6aa87a3b12 100644 --- a/arch/powerpc/kernel/process.c +++ b/arch/powerpc/kernel/process.c @@ -854,7 +854,7 @@ void restore_tm_state(struct pt_regs *regs) static inline void save_sprs(struct thread_struct *t) { #ifdef CONFIG_ALTIVEC - if (cpu_has_feature(cpu_has_feature(CPU_FTR_ALTIVEC))) + if (cpu_has_feature(CPU_FTR_ALTIVEC)) t->vrsave = mfspr(SPRN_VRSAVE); #endif #ifdef CONFIG_PPC_BOOK3S_64