diff mbox

powerpc/process: fix altivec SPR not being saved

Message ID 1457303588-29173-1-git-send-email-oohall@gmail.com (mailing list archive)
State Superseded
Headers show

Commit Message

Oliver O'Halloran March 6, 2016, 10:33 p.m. UTC
In save_sprs() in process.c contains the following test:

	if (cpu_has_feature(cpu_has_feature(CPU_FTR_ALTIVEC)))
		t->vrsave = mfspr(SPRN_VRSAVE);

CPU feature with the mask 0x1 is CPU_FTR_COHERENT_ICACHE so the test
is equivilent to:

	if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
		cpu_has_feature(CPU_FTR_COHERENT_ICACHE))

On CPUs without support for both (i.e G5) this results in vrsave not being
saved between context switches. The vector register save/restore code
doesn't use VRSAVE to determine which registers to save/restore,
but the value of VRSAVE is used to determine if altivec is being used
in several code paths.

Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
---
 arch/powerpc/kernel/process.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Benjamin Herrenschmidt March 7, 2016, 3:51 a.m. UTC | #1
On Mon, 2016-03-07 at 09:33 +1100, Oliver O'Halloran wrote:
> In save_sprs() in process.c contains the following test:
> 
> 	if (cpu_has_feature(cpu_has_feature(CPU_FTR_ALTIVEC)))
> 		t->vrsave = mfspr(SPRN_VRSAVE);
> 
> CPU feature with the mask 0x1 is CPU_FTR_COHERENT_ICACHE so the test
> is equivilent to:
> 
> 	if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
> 		cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
> 
> On CPUs without support for both (i.e G5) this results in vrsave not
> being
> saved between context switches. The vector register save/restore code
> doesn't use VRSAVE to determine which registers to save/restore,
> but the value of VRSAVE is used to determine if altivec is being used
> in several code paths.

Nice one, should probably go to stable !

> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
> ---
>  arch/powerpc/kernel/process.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/powerpc/kernel/process.c
> b/arch/powerpc/kernel/process.c
> index 8224852..5a4d4d1 100644
> --- a/arch/powerpc/kernel/process.c
> +++ b/arch/powerpc/kernel/process.c
> @@ -855,7 +855,7 @@ void restore_tm_state(struct pt_regs *regs)
>  static inline void save_sprs(struct thread_struct *t)
>  {
>  #ifdef CONFIG_ALTIVEC
> -	if (cpu_has_feature(cpu_has_feature(CPU_FTR_ALTIVEC)))
> +	if (cpu_has_feature(CPU_FTR_ALTIVEC))
>  		t->vrsave = mfspr(SPRN_VRSAVE);
>  #endif
>  #ifdef CONFIG_PPC_BOOK3S_64
Unknown sender due to SPF March 7, 2016, 4:19 a.m. UTC | #2
Hi Oliver,

> In save_sprs() in process.c contains the following test:
> 
> 	if (cpu_has_feature(cpu_has_feature(CPU_FTR_ALTIVEC)))
> 		t->vrsave = mfspr(SPRN_VRSAVE);
> 
> CPU feature with the mask 0x1 is CPU_FTR_COHERENT_ICACHE so the test
> is equivilent to:
> 
> 	if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
> 		cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
> 
> On CPUs without support for both (i.e G5) this results in vrsave not
> being saved between context switches. The vector register
> save/restore code doesn't use VRSAVE to determine which registers to
> save/restore, but the value of VRSAVE is used to determine if altivec
> is being used in several code paths.

Nice catch, not sure how I missed that. As Ben suggests, it should
definitely go to -stable as well.

Feel free to add my sign off:

Signed-off-by: Anton Blanchard <anton@samba.org>

Anton

> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
> ---
>  arch/powerpc/kernel/process.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/powerpc/kernel/process.c
> b/arch/powerpc/kernel/process.c index 8224852..5a4d4d1 100644
> --- a/arch/powerpc/kernel/process.c
> +++ b/arch/powerpc/kernel/process.c
> @@ -855,7 +855,7 @@ void restore_tm_state(struct pt_regs *regs)
>  static inline void save_sprs(struct thread_struct *t)
>  {
>  #ifdef CONFIG_ALTIVEC
> -	if (cpu_has_feature(cpu_has_feature(CPU_FTR_ALTIVEC)))
> +	if (cpu_has_feature(CPU_FTR_ALTIVEC))
>  		t->vrsave = mfspr(SPRN_VRSAVE);
>  #endif
>  #ifdef CONFIG_PPC_BOOK3S_64
diff mbox

Patch

diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 8224852..5a4d4d1 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -855,7 +855,7 @@  void restore_tm_state(struct pt_regs *regs)
 static inline void save_sprs(struct thread_struct *t)
 {
 #ifdef CONFIG_ALTIVEC
-	if (cpu_has_feature(cpu_has_feature(CPU_FTR_ALTIVEC)))
+	if (cpu_has_feature(CPU_FTR_ALTIVEC))
 		t->vrsave = mfspr(SPRN_VRSAVE);
 #endif
 #ifdef CONFIG_PPC_BOOK3S_64