| Message ID | 1453710826-3160-1-git-send-email-maddy@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
On 01/25/2016 02:03 PM, Madhavan Srinivasan wrote: > Commit: 7a7868326d77 introduced PPMU_HAS_SSLOT flag to > remove assumption of MMCRA[SLOT] with respect to > PPMU_ALT_SIPR flag. Commit 7a7868326d77's message also > specifies that Power8 does not support MMCRA[SLOT]. > But still PPMU_HAS_SSLOT flag managed to get into > Power8 code. Patch to remove the same from Power8 flags. Please follow the present protocol of referring to a commit ID like this (<hash_code>: ""). Also this PMU flag was added originally through the base POWER8 PMU enablement commit (e05b9b9e5c1: "powerpc/perf: Power8 PMU support") which can be mentioned in the "Fixes:" part.
On Mon, 2016-01-25 at 14:03 +0530, Madhavan Srinivasan wrote: > Commit: 7a7868326d77 introduced PPMU_HAS_SSLOT flag to > remove assumption of MMCRA[SLOT] with respect to > PPMU_ALT_SIPR flag. Commit 7a7868326d77's message also > specifies that Power8 does not support MMCRA[SLOT]. > But still PPMU_HAS_SSLOT flag managed to get into > Power8 code. Patch to remove the same from Power8 flags. > > Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Thanks. I cleaned up and expanded the change log: powerpc/perf: Remove PPMU_HAS_SSLOT flag for Power8 Commit 7a7868326d77 ("powerpc/perf: Add an explict flag indicating presence of SLOT field") introduced the PPMU_HAS_SSLOT flag to remove the assumption that MMCRA[SLOT] was present when PPMU_ALT_SIPR was not set. That commit's changelog also mentions that Power8 does not support MMCRA[SLOT]. However when the Power8 PMU support was merged, it errnoeously included the PPMU_HAS_SSLOT flag. So remove PPMU_HAS_SSLOT from the Power8 flags. mpe: On systems where MMCRA[SLOT] exists, the field occupies bits 37:39 (IBM numbering). On Power8 bit 37 is reserved, and 38:39 overlap with the high bits of the Threshold Event Counter Mantissa. I am not aware of any published events which use the thereshold counting mechanism, which would cause the mantissa bits to be set. So in practice this bug is unlikely to trigger in practice. Fixes: e05b9b9e5c10 ("powerpc/perf: Power8 PMU support") Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> cheers
On Mon, 2016-25-01 at 08:33:46 UTC, Madhavan Srinivasan wrote: > Commit: 7a7868326d77 introduced PPMU_HAS_SSLOT flag to > remove assumption of MMCRA[SLOT] with respect to > PPMU_ALT_SIPR flag. Commit 7a7868326d77's message also > specifies that Power8 does not support MMCRA[SLOT]. > But still PPMU_HAS_SSLOT flag managed to get into > Power8 code. Patch to remove the same from Power8 flags. > > Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Applied to powerpc fixes, thanks. https://git.kernel.org/powerpc/c/370f06c88528b3988fe24a372c cheers
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c index 7d5e295255b7..9958ba8bf0d2 100644 --- a/arch/powerpc/perf/power8-pmu.c +++ b/arch/powerpc/perf/power8-pmu.c @@ -816,7 +816,7 @@ static struct power_pmu power8_pmu = { .get_constraint = power8_get_constraint, .get_alternatives = power8_get_alternatives, .disable_pmc = power8_disable_pmc, - .flags = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_ARCH_207S, + .flags = PPMU_HAS_SIER | PPMU_ARCH_207S, .n_generic = ARRAY_SIZE(power8_generic_events), .generic_events = power8_generic_events, .cache_events = &power8_cache_events,
Commit: 7a7868326d77 introduced PPMU_HAS_SSLOT flag to remove assumption of MMCRA[SLOT] with respect to PPMU_ALT_SIPR flag. Commit 7a7868326d77's message also specifies that Power8 does not support MMCRA[SLOT]. But still PPMU_HAS_SSLOT flag managed to get into Power8 code. Patch to remove the same from Power8 flags. Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> --- arch/powerpc/perf/power8-pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)