From patchwork Thu Jun 11 05:17:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: maddy X-Patchwork-Id: 482970 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id AC7AE140290 for ; Thu, 11 Jun 2015 15:23:03 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 8EF681A1AB6 for ; Thu, 11 Jun 2015 15:23:03 +1000 (AEST) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from e28smtp06.in.ibm.com (e28smtp06.in.ibm.com [122.248.162.6]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 24E111A0E07 for ; Thu, 11 Jun 2015 15:18:15 +1000 (AEST) Received: from /spool/local by e28smtp06.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 11 Jun 2015 10:48:12 +0530 Received: from d28relay02.in.ibm.com (d28relay02.in.ibm.com [9.184.220.59]) by d28dlp03.in.ibm.com (Postfix) with ESMTP id 4562B1258053 for ; Thu, 11 Jun 2015 10:50:42 +0530 (IST) Received: from d28av04.in.ibm.com (d28av04.in.ibm.com [9.184.220.66]) by d28relay02.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t5B5I7Oc9175154 for ; Thu, 11 Jun 2015 10:48:08 +0530 Received: from d28av04.in.ibm.com (localhost [127.0.0.1]) by d28av04.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t5B5I66m001113 for ; Thu, 11 Jun 2015 10:48:07 +0530 Received: from SrihariMadhavan.ibm.com ([9.79.146.172]) by d28av04.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t5B5HwFK000506; Thu, 11 Jun 2015 10:48:05 +0530 From: Madhavan Srinivasan To: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: [PATCH v2 3/7]powerpc/powernv: Nest PMU detection and device tree parser Date: Thu, 11 Jun 2015 10:47:50 +0530 Message-Id: <1433999874-2043-4-git-send-email-maddy@linux.vnet.ibm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1433999874-2043-1-git-send-email-maddy@linux.vnet.ibm.com> References: <1433999874-2043-1-git-send-email-maddy@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15061105-0021-0000-0000-000005B6985B X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Madhavan Srinivasan , rusty@rustcorp.com.au, Stephane Eranian , Paul Mackerras , Anton Blanchard , Sukadev Bhattiprolu , Anshuman Khandual MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Create a file "nest-pmu.c" to contain nest pmu related functions. Code to detect nest pmu support and parser to collect per-chip reserved memory region information from device tree (DT). Detection mechanism is to look for specific property "ibm,ima-chip" in DT. For Nest pmu, device tree will have two set of information. 1) Per-chip reserved memory region for nest pmu counter collection area. 2) Supported Nest PMUs and events Device tree layout for the Nest PMU as follows. / -- DT root folder | -nest-ima -- Nest PMU folder | -ima-chip@ -- Per-chip folder for reserved region information | -ibm,chip-id -- Chip id -ibm,ima-chip -reg -- HOMER PORE Nest Counter collection Address (RA) -size -- size to map in kernel space -Alink_BW -- Nest PMU folder | -Alink0 -- Nest PMU Alink Event file -scale.Alink0.scale -- Event scale file -unit.Alink0.unit -- Event unit file -device_type -- "nest-ima-unit" marker .... Subsequent patch will parse the next part of the DT to find various Nest PMUs and their events. Cc: Michael Ellerman Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: Anton Blanchard Cc: Sukadev Bhattiprolu Cc: Anshuman Khandual Cc: Stephane Eranian Signed-off-by: Madhavan Srinivasan --- arch/powerpc/perf/Makefile | 2 +- arch/powerpc/perf/nest-pmu.c | 78 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 arch/powerpc/perf/nest-pmu.c diff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf/Makefile index f9c083a..6da656b 100644 --- a/arch/powerpc/perf/Makefile +++ b/arch/powerpc/perf/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_PERF_EVENTS) += callchain.o obj-$(CONFIG_PPC_PERF_CTRS) += core-book3s.o bhrb.o obj64-$(CONFIG_PPC_PERF_CTRS) += power4-pmu.o ppc970-pmu.o power5-pmu.o \ power5+-pmu.o power6-pmu.o power7-pmu.o \ - power8-pmu.o + power8-pmu.o nest-pmu.o obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o obj-$(CONFIG_FSL_EMB_PERF_EVENT) += core-fsl-emb.o diff --git a/arch/powerpc/perf/nest-pmu.c b/arch/powerpc/perf/nest-pmu.c new file mode 100644 index 0000000..e993630 --- /dev/null +++ b/arch/powerpc/perf/nest-pmu.c @@ -0,0 +1,78 @@ +/* + * Nest Performance Monitor counter support for POWER8 processors. + * + * Copyright (C) 2015 Madhavan Srinivasan, IBM Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "nest-pmu.h" + +static struct perchip_nest_info p8_perchip_nest_info[P8_MAX_CHIP]; + +static int nest_ima_dt_parser(void) +{ + const __be32 *gcid; + const __be64 *chip_ima_reg; + const __be64 *chip_ima_size; + struct device_node *dev; + int idx; + + /* + * "nest-ima" folder contains two things, + * a) per-chip reserved memory region for Nest PMU Counter data + * b) Support Nest PMU units and their event files + */ + for_each_node_with_property(dev, "ibm,ima-chip") { + gcid = of_get_property(dev, "ibm,chip-id", NULL); + chip_ima_reg = of_get_property(dev, "reg", NULL); + chip_ima_size = of_get_property(dev, "size", NULL); + if ((!gcid) || (!chip_ima_reg) || (!chip_ima_size)) { + pr_err("Nest_PMU: device %s missing property \n", + dev->full_name); + return -ENODEV; + } + + /* Save per-chip reserve memory region */ + idx = (uint32_t)be32_to_cpup(gcid); + p8_perchip_nest_info[idx].pbase = be64_to_cpup(chip_ima_reg); + p8_perchip_nest_info[idx].size = be64_to_cpup(chip_ima_size); + p8_perchip_nest_info[idx].vbase = (uint64_t) + phys_to_virt(p8_perchip_nest_info[idx].pbase); + } + + return 0; +} + +static int __init nest_pmu_init(void) +{ + int ret = -ENODEV; + + /* + * Lets do this only if we are hypervisor + */ + if (!cur_cpu_spec->oprofile_cpu_type || + !(strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power8") == 0) || + !cpu_has_feature(CPU_FTR_HVMODE)) + return ret; + + /* + * Nest PMU information are grouped under "nest-ima" node + * of the top-level Device-Tree directory. Detect Nest PMU + * with "ibm,ima-chip" property. + */ + if (!of_find_node_with_property(NULL, "ibm,ima-chip")) + return ret; + + /* + * Parser Device-tree for Nest PMU information + */ + ret = nest_ima_dt_parser(); + if (ret) + return ret; + + return 0; +} +device_initcall(nest_pmu_init);