From patchwork Thu Jun 11 05:17:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: maddy X-Patchwork-Id: 482968 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6FF9014007F for ; Thu, 11 Jun 2015 15:20:31 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 569501A0F51 for ; Thu, 11 Jun 2015 15:20:31 +1000 (AEST) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from e28smtp05.in.ibm.com (e28smtp05.in.ibm.com [122.248.162.5]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 1AD051A09FE for ; Thu, 11 Jun 2015 15:18:09 +1000 (AEST) Received: from /spool/local by e28smtp05.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 11 Jun 2015 10:48:04 +0530 Received: from d28relay03.in.ibm.com (d28relay03.in.ibm.com [9.184.220.60]) by d28dlp01.in.ibm.com (Postfix) with ESMTP id 5464CE0056 for ; Thu, 11 Jun 2015 10:51:27 +0530 (IST) Received: from d28av04.in.ibm.com (d28av04.in.ibm.com [9.184.220.66]) by d28relay03.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t5B5I3Th000470 for ; Thu, 11 Jun 2015 10:48:03 +0530 Received: from d28av04.in.ibm.com (localhost [127.0.0.1]) by d28av04.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t5B5I1st000776 for ; Thu, 11 Jun 2015 10:48:02 +0530 Received: from SrihariMadhavan.ibm.com ([9.79.146.172]) by d28av04.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t5B5HwFI000506; Thu, 11 Jun 2015 10:48:00 +0530 From: Madhavan Srinivasan To: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: [PATCH v2 1/7]powerpc/powernv: Data structure and macros definition Date: Thu, 11 Jun 2015 10:47:48 +0530 Message-Id: <1433999874-2043-2-git-send-email-maddy@linux.vnet.ibm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1433999874-2043-1-git-send-email-maddy@linux.vnet.ibm.com> References: <1433999874-2043-1-git-send-email-maddy@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15061105-0017-0000-0000-0000059930B0 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Madhavan Srinivasan , rusty@rustcorp.com.au, Stephane Eranian , Paul Mackerras , Anton Blanchard , Sukadev Bhattiprolu , Anshuman Khandual MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" Create new header file "nest-pmu.h" to add the data structures and macros needed for the nest pmu support. Cc: Michael Ellerman Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: Anton Blanchard Cc: Sukadev Bhattiprolu Cc: Anshuman Khandual Cc: Stephane Eranian Signed-off-by: Madhavan Srinivasan --- arch/powerpc/perf/nest-pmu.h | 53 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 arch/powerpc/perf/nest-pmu.h diff --git a/arch/powerpc/perf/nest-pmu.h b/arch/powerpc/perf/nest-pmu.h new file mode 100644 index 0000000..ebe7689 --- /dev/null +++ b/arch/powerpc/perf/nest-pmu.h @@ -0,0 +1,53 @@ +/* + * Nest Performance Monitor counter support for POWER8 processors. + * + * Copyright (C) 2015 Madhavan Srinivasan, IBM Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#define P8_MAX_CHIP 32 +#define MAX_PMU_NAME_LEN 256 +#define MAX_EVENTS_SUPPORTED 256 +#define P8_NEST_ENGINE_START 1 +#define P8_NEST_ENGINE_STOP 0 +#define P8_MAX_NEST_PMUS 32 + +/* + * Structure to hold per chip specific memory address + * information for nest pmus. Nest Counter data are exported + * in per-chip reserved memory region by the PORE Engine. + */ +struct perchip_nest_info { + uint32_t chip_id; + uint64_t pbase; + uint64_t vbase; + uint32_t size; +}; + +/* + * Place holder for nest pmu events and values. + */ +struct ppc64_nest_ima_events { + const char *ev_name; + const char *ev_value; +}; + +/* + * Device tree parser code detects nest pmu support and + * registers new nest pmus. This structure will + * hold the pmu functions and attrs for each nest pmu and + * will be referenced at the time of pmu registration. + */ +struct nest_pmu { + struct pmu pmu; + const struct attribute_group *attr_groups[4]; +};