From patchwork Thu Mar 26 09:16:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ying.zhang@freescale.com X-Patchwork-Id: 454975 X-Patchwork-Delegate: scottwood@freescale.com Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C9DDD14012F for ; Thu, 26 Mar 2015 22:55:43 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 9DBCD1A06B9 for ; Thu, 26 Mar 2015 22:55:43 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org X-Greylist: delayed 976 seconds by postgrey-1.35 at bilbo; Thu, 26 Mar 2015 21:23:44 AEDT Received: from na01-bl2-obe.outbound.protection.outlook.com (mail-bl2on0119.outbound.protection.outlook.com [65.55.169.119]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 392B41A0689 for ; Thu, 26 Mar 2015 21:23:43 +1100 (AEDT) Received: from BN3PR0301CA0011.namprd03.prod.outlook.com (25.160.180.149) by CY1PR0301MB1308.namprd03.prod.outlook.com (25.161.212.18) with Microsoft SMTP Server (TLS) id 15.1.118.21; Thu, 26 Mar 2015 10:08:20 +0000 Received: from BN1BFFO11FD056.protection.gbl (2a01:111:f400:7c10::1:199) by BN3PR0301CA0011.outlook.office365.com (2a01:111:e400:4000::21) with Microsoft SMTP Server (TLS) id 15.1.125.19 via Frontend Transport; Thu, 26 Mar 2015 10:08:19 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1BFFO11FD056.mail.protection.outlook.com (10.58.145.11) with Microsoft SMTP Server (TLS) id 15.1.125.13 via Frontend Transport; Thu, 26 Mar 2015 10:08:19 +0000 Received: from Tank.ap.freescale.net (tank.ap.freescale.net [10.193.20.104]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id t2QA8FE6031083; Thu, 26 Mar 2015 03:08:16 -0700 From: To: , Subject: [PATCH 3/3] P1021RDB: Add QE TDM support Date: Thu, 26 Mar 2015 17:16:17 +0800 Message-ID: <1427361377-4789-1-git-send-email-ying.zhang@freescale.com> X-Mailer: git-send-email 1.8.4.1 X-EOPAttributedMessage: 0 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=ying.zhang@freescale.com; mgd.freescale.com; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI; BMV:1; SFV:NSPM; SFS:(10019020)(6009001)(339900001)(199003)(189002)(87936001)(6806004)(86152002)(50226001)(50466002)(47776003)(105606002)(36756003)(229853001)(48376002)(19580405001)(77156002)(62966003)(450100001)(50986999)(33646002)(106466001)(86362001)(77096005)(85426001)(19580395003)(92566002)(46102003)(104016003); DIR:OUT; SFP:1102; SCL:1; SRVR:CY1PR0301MB1308; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; MLV:sfv; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR0301MB1308; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(5002010); SRVR:CY1PR0301MB1308; BCL:0; PCL:0; RULEID:; SRVR:CY1PR0301MB1308; X-Forefront-PRVS: 0527DFA348 X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2015 10:08:19.9232 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR0301MB1308 X-Mailman-Approved-At: Thu, 26 Mar 2015 22:54:41 +1100 Cc: Xie Xiaobo , Ying Zhang X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Ying Zhang The P1021RDB-PC have PMC sockets that support QE-TDM function. The patch enable Quicc Engine and the related signals of QE-TDM. Signed-off-by: Ying Zhang Signed-off-by: Xie Xiaobo Signed-off-by: Li Yang --- arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 76 ++++++++++++++++++++++--------- 1 file changed, 54 insertions(+), 22 deletions(-) diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c index e358bed..a2f0639 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c @@ -86,6 +86,12 @@ void __init mpc85xx_rdb_pic_init(void) */ static void __init mpc85xx_rdb_setup_arch(void) { + struct device_node *np; +#if defined(CONFIG_QUICC_ENGINE) && defined(CONFIG_SPI_FSL_SPI) + struct device_node *qe_spi; +#endif + struct ccsr_guts __iomem *guts; + if (ppc_md.progress) ppc_md.progress("mpc85xx_rdb_setup_arch()", 0); @@ -96,37 +102,63 @@ static void __init mpc85xx_rdb_setup_arch(void) #ifdef CONFIG_QUICC_ENGINE mpc85xx_qe_init(); mpc85xx_qe_par_io_init(); -#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) - if (machine_is(p1025_rdb)) { - struct device_node *np; - - struct ccsr_guts __iomem *guts; - - np = of_find_node_by_name(NULL, "global-utilities"); - if (np) { - guts = of_iomap(np, 0); - if (!guts) { - - pr_err("mpc85xx-rdb: could not map global utilities register\n"); +#ifdef CONFIG_SPI_FSL_SPI + for_each_node_by_name(qe_spi, "spi") + par_io_of_config(qe_spi); +#endif /* CONFIG_SPI_FSL_SPI */ - } else { - /* P1025 has pins muxed for QE and other functions. To - * enable QE UEC mode, we need to set bit QE0 for UCC1 - * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 - * and QE12 for QE MII management singals in PMUXCR - * register. - */ + np = of_find_node_by_name(NULL, "global-utilities"); + if (np) { + guts = of_iomap(np, 0); + if (!guts) + pr_err("mpc85xx-rdb: could not map global %s\n", + "utilities register"); + else { +#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) + if (machine_is(p1025_rdb)) { + /* + * P1025 has pins muxed for QE and other + * functions. To enable QE UEC mode, we + * need to set bit QE0 for UCC1 in Eth mode, + * QE0 and QE3 for UCC5 in Eth mode, QE9 + * and QE12 for QE MII management singals + * in PMUXCR register. + */ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | MPC85xx_PMUXCR_QE(3) | MPC85xx_PMUXCR_QE(9) | MPC85xx_PMUXCR_QE(12)); - iounmap(guts); } - of_node_put(np); +#endif +#ifdef CONFIG_FSL_UCC_TDM + if (machine_is(p1021_rdb_pc)) { + /* Clear QE12 for releasing the LBCTL */ + clrbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(12)); + /* TDMA */ + setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(5) | + MPC85xx_PMUXCR_QE(11)); + /* TDMB */ + setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | + MPC85xx_PMUXCR_QE(9)); + /* TDMC */ + setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0)); + /* TDMD */ + setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(8) | + MPC85xx_PMUXCR_QE(7)); + } +#endif /* CONFIG_FSL_UCC_TDM */ +#ifdef CONFIG_SPI_FSL_SPI + clrbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(12)); + /*QE-SPI*/ + setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(6) | + MPC85xx_PMUXCR_QE(9) | + MPC85xx_PMUXCR_QE(10)); +#endif /* CONFIG_SPI_FSL_SPI */ + iounmap(guts); } + of_node_put(np); } -#endif #endif /* CONFIG_QUICC_ENGINE */ printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");