diff mbox

powerpc: book3e_64: fix the align size for paca_struct

Message ID 1425726893-30605-1-git-send-email-haokexin@gmail.com (mailing list archive)
State Accepted
Commit 016f8cf0d87bb2bda15ccb8708748a013c27423f
Headers show

Commit Message

Kevin Hao March 7, 2015, 11:14 a.m. UTC
All the cache line size of the current book3e 64bit SoCs are 64 bytes.
So we should use this size to align the member of paca_struct.
With this change we save 192 bytes. Also change it to __aligned(size)
since it is preferred over __attribute__((aligned(size))).

Before:
	/* size: 1920, cachelines: 30, members: 46 */
	/* sum members: 1667, holes: 6, sum holes: 141 */
	/* padding: 112 */

After:
	/* size: 1728, cachelines: 27, members: 46 */
	/* sum members: 1667, holes: 4, sum holes: 13 */
	/* padding: 48 */

Signed-off-by: Kevin Hao <haokexin@gmail.com>
---
 arch/powerpc/include/asm/paca.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Benjamin Herrenschmidt March 8, 2015, 9:13 a.m. UTC | #1
On Sat, 2015-03-07 at 19:14 +0800, Kevin Hao wrote:
> All the cache line size of the current book3e 64bit SoCs are 64 bytes.
> So we should use this size to align the member of paca_struct.
> With this change we save 192 bytes. Also change it to __aligned(size)
> since it is preferred over __attribute__((aligned(size))).

Why should we favor the book3e CPUs over the book3s ones ? Since we
can't build a kernel that deals with both, make it a compile option.

> Before:
> 	/* size: 1920, cachelines: 30, members: 46 */
> 	/* sum members: 1667, holes: 6, sum holes: 141 */
> 	/* padding: 112 */
> 
> After:
> 	/* size: 1728, cachelines: 27, members: 46 */
> 	/* sum members: 1667, holes: 4, sum holes: 13 */
> 	/* padding: 48 */
> 
> Signed-off-by: Kevin Hao <haokexin@gmail.com>
> ---
>  arch/powerpc/include/asm/paca.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
> index e5f22c6c4bf9..70bd4381f8e6 100644
> --- a/arch/powerpc/include/asm/paca.h
> +++ b/arch/powerpc/include/asm/paca.h
> @@ -106,9 +106,9 @@ struct paca_struct {
>  #endif /* CONFIG_PPC_STD_MMU_64 */
>  
>  #ifdef CONFIG_PPC_BOOK3E
> -	u64 exgen[8] __attribute__((aligned(0x80)));
> +	u64 exgen[8] __aligned(0x40);
>  	/* Keep pgd in the same cacheline as the start of extlb */
> -	pgd_t *pgd __attribute__((aligned(0x80))); /* Current PGD */
> +	pgd_t *pgd __aligned(0x40); /* Current PGD */
>  	pgd_t *kernel_pgd;		/* Kernel PGD */
>  
>  	/* Shared by all threads of a core -- points to tcd of first thread */
Kevin Hao March 9, 2015, 1:13 a.m. UTC | #2
On Sun, Mar 08, 2015 at 08:13:26PM +1100, Benjamin Herrenschmidt wrote:
> On Sat, 2015-03-07 at 19:14 +0800, Kevin Hao wrote:
> > All the cache line size of the current book3e 64bit SoCs are 64 bytes.
> > So we should use this size to align the member of paca_struct.
> > With this change we save 192 bytes. Also change it to __aligned(size)
> > since it is preferred over __attribute__((aligned(size))).
> 
> Why should we favor the book3e CPUs over the book3s ones ?

Why do you think so? This only change the align size of the paca_struct's
members which are private to book3e CPUs, and should not have any effect
to book3s ones. Did I miss something?

Thanks,
Kevin
Benjamin Herrenschmidt March 9, 2015, 7:31 a.m. UTC | #3
On Mon, 2015-03-09 at 09:13 +0800, Kevin Hao wrote:
> On Sun, Mar 08, 2015 at 08:13:26PM +1100, Benjamin Herrenschmidt wrote:
> > On Sat, 2015-03-07 at 19:14 +0800, Kevin Hao wrote:
> > > All the cache line size of the current book3e 64bit SoCs are 64 bytes.
> > > So we should use this size to align the member of paca_struct.
> > > With this change we save 192 bytes. Also change it to __aligned(size)
> > > since it is preferred over __attribute__((aligned(size))).
> > 
> > Why should we favor the book3e CPUs over the book3s ones ?
> 
> Why do you think so? This only change the align size of the paca_struct's
> members which are private to book3e CPUs, and should not have any effect
> to book3s ones. Did I miss something?

No, your explanation was lacking that important detail :-)

> Thanks,
> Kevin
Kevin Hao March 10, 2015, 12:21 p.m. UTC | #4
On Mon, Mar 09, 2015 at 06:31:25PM +1100, Benjamin Herrenschmidt wrote:
> On Mon, 2015-03-09 at 09:13 +0800, Kevin Hao wrote:
> > On Sun, Mar 08, 2015 at 08:13:26PM +1100, Benjamin Herrenschmidt wrote:
> > > On Sat, 2015-03-07 at 19:14 +0800, Kevin Hao wrote:
> > > > All the cache line size of the current book3e 64bit SoCs are 64 bytes.
> > > > So we should use this size to align the member of paca_struct.
> > > > With this change we save 192 bytes. Also change it to __aligned(size)
> > > > since it is preferred over __attribute__((aligned(size))).
> > > 
> > > Why should we favor the book3e CPUs over the book3s ones ?
> > 
> > Why do you think so? This only change the align size of the paca_struct's
> > members which are private to book3e CPUs, and should not have any effect
> > to book3s ones. Did I miss something?
> 
> No, your explanation was lacking that important detail :-)

Sorry for the confusion, I will add this information in the commit log.

Thanks,
Kevin
diff mbox

Patch

diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index e5f22c6c4bf9..70bd4381f8e6 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -106,9 +106,9 @@  struct paca_struct {
 #endif /* CONFIG_PPC_STD_MMU_64 */
 
 #ifdef CONFIG_PPC_BOOK3E
-	u64 exgen[8] __attribute__((aligned(0x80)));
+	u64 exgen[8] __aligned(0x40);
 	/* Keep pgd in the same cacheline as the start of extlb */
-	pgd_t *pgd __attribute__((aligned(0x80))); /* Current PGD */
+	pgd_t *pgd __aligned(0x40); /* Current PGD */
 	pgd_t *kernel_pgd;		/* Kernel PGD */
 
 	/* Shared by all threads of a core -- points to tcd of first thread */