diff mbox

[1/3] powerpc/mpc85xx: Add FMan clock nodes

Message ID 1424964417-13760-1-git-send-email-Emilian.Medve@Freescale.com
State Rejected
Delegated to: Scott Wood
Headers show

Commit Message

Emil Medve Feb. 26, 2015, 3:26 p.m. UTC
From: Igal Liberman <Igal.Liberman@freescale.com>

Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
---
 arch/powerpc/boot/dts/fsl/b4si-post.dtsi    | 11 +++++++++++
 arch/powerpc/boot/dts/fsl/p2041si-post.dtsi |  8 ++++++++
 arch/powerpc/boot/dts/fsl/p3041si-post.dtsi |  8 ++++++++
 arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 16 ++++++++++++++++
 arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 13 +++++++++++++
 arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 26 ++++++++++++++++++++++++++
 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi |  8 ++++++++
 arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 11 +++++++++++
 arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 20 ++++++++++++++++++++
 9 files changed, 121 insertions(+)

Comments

Scott Wood March 23, 2015, 11:30 p.m. UTC | #1
On Thu, 2015-02-26 at 09:26 -0600, Emil Medve wrote:
> From: Igal Liberman <Igal.Liberman@freescale.com>
> 
> Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
> ---
>  arch/powerpc/boot/dts/fsl/b4si-post.dtsi    | 11 +++++++++++
>  arch/powerpc/boot/dts/fsl/p2041si-post.dtsi |  8 ++++++++
>  arch/powerpc/boot/dts/fsl/p3041si-post.dtsi |  8 ++++++++
>  arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 16 ++++++++++++++++
>  arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 13 +++++++++++++
>  arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 26 ++++++++++++++++++++++++++
>  arch/powerpc/boot/dts/fsl/t1040si-post.dtsi |  8 ++++++++
>  arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 11 +++++++++++
>  arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 20 ++++++++++++++++++++
>  9 files changed, 121 insertions(+)
> 
> diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> index f8c325e..38621ef 100644
> --- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> @@ -395,6 +395,17 @@
>  		reg = <0xe0000 0xe00>;
>  		fsl,has-rstcr;
>  		fsl,liodn-bits = <12>;
> +
> +		fm0clk: fm0-clk-mux {
> +			#clock-cells = <0>;
> +			compatible = "fsl,fman-clk-mux";
> +			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll0 3>,
> +				 <&platform_pll 0>, <&pll1 1>, <&pll1 2>;
> +			clock-names = "pll0", "pll0-div2", "pll0-div3",
> +				      "pll0-div4", "platform-pll", "pll1-div2",
> +				      "pll1-div3";
> +			clock-output-names = "fm0-clk";
> +		};

Where's the binding for fsl,fman-clk-mux?

-Scott
Emil Medve March 24, 2015, 8:26 a.m. UTC | #2
Hello Scott,


On 03/23/2015 06:30 PM, Scott Wood wrote:
> On Thu, 2015-02-26 at 09:26 -0600, Emil Medve wrote:
>> From: Igal Liberman <Igal.Liberman@freescale.com>
>>
>> Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
>> ---
>>  arch/powerpc/boot/dts/fsl/b4si-post.dtsi    | 11 +++++++++++
>>  arch/powerpc/boot/dts/fsl/p2041si-post.dtsi |  8 ++++++++
>>  arch/powerpc/boot/dts/fsl/p3041si-post.dtsi |  8 ++++++++
>>  arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 16 ++++++++++++++++
>>  arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 13 +++++++++++++
>>  arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 26 ++++++++++++++++++++++++++
>>  arch/powerpc/boot/dts/fsl/t1040si-post.dtsi |  8 ++++++++
>>  arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 11 +++++++++++
>>  arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 20 ++++++++++++++++++++
>>  9 files changed, 121 insertions(+)
>>
>> diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
>> index f8c325e..38621ef 100644
>> --- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
>> +++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
>> @@ -395,6 +395,17 @@
>>  		reg = <0xe0000 0xe00>;
>>  		fsl,has-rstcr;
>>  		fsl,liodn-bits = <12>;
>> +
>> +		fm0clk: fm0-clk-mux {
>> +			#clock-cells = <0>;
>> +			compatible = "fsl,fman-clk-mux";
>> +			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll0 3>,
>> +				 <&platform_pll 0>, <&pll1 1>, <&pll1 2>;
>> +			clock-names = "pll0", "pll0-div2", "pll0-div3",
>> +				      "pll0-div4", "platform-pll", "pll1-div2",
>> +				      "pll1-div3";
>> +			clock-output-names = "fm0-clk";
>> +		};
> 
> Where's the binding for fsl,fman-clk-mux?
> 

Igal will follow-up with the binding document


Cheers,
Scott Wood March 31, 2015, 12:15 a.m. UTC | #3
On Tue, 2015-03-24 at 03:26 -0500, Emil Medve wrote:
> Hello Scott,
> 
> 
> On 03/23/2015 06:30 PM, Scott Wood wrote:
> > On Thu, 2015-02-26 at 09:26 -0600, Emil Medve wrote:
> >> From: Igal Liberman <Igal.Liberman@freescale.com>
> >>
> >> Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
> >> ---
> >>  arch/powerpc/boot/dts/fsl/b4si-post.dtsi    | 11 +++++++++++
> >>  arch/powerpc/boot/dts/fsl/p2041si-post.dtsi |  8 ++++++++
> >>  arch/powerpc/boot/dts/fsl/p3041si-post.dtsi |  8 ++++++++
> >>  arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 16 ++++++++++++++++
> >>  arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 13 +++++++++++++
> >>  arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 26 ++++++++++++++++++++++++++
> >>  arch/powerpc/boot/dts/fsl/t1040si-post.dtsi |  8 ++++++++
> >>  arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 11 +++++++++++
> >>  arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 20 ++++++++++++++++++++
> >>  9 files changed, 121 insertions(+)
> >>
> >> diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> >> index f8c325e..38621ef 100644
> >> --- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> >> +++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> >> @@ -395,6 +395,17 @@
> >>  		reg = <0xe0000 0xe00>;
> >>  		fsl,has-rstcr;
> >>  		fsl,liodn-bits = <12>;
> >> +
> >> +		fm0clk: fm0-clk-mux {
> >> +			#clock-cells = <0>;
> >> +			compatible = "fsl,fman-clk-mux";
> >> +			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll0 3>,
> >> +				 <&platform_pll 0>, <&pll1 1>, <&pll1 2>;
> >> +			clock-names = "pll0", "pll0-div2", "pll0-div3",
> >> +				      "pll0-div4", "platform-pll", "pll1-div2",
> >> +				      "pll1-div3";
> >> +			clock-output-names = "fm0-clk";
> >> +		};
> > 
> > Where's the binding for fsl,fman-clk-mux?
> > 
> 
> Igal will follow-up with the binding document

Igal, ping?

I need a binding before I can apply the dts patch.

-Scott
Igal.Liberman March 31, 2015, 6:17 a.m. UTC | #4
> -----Original Message-----

> From: Wood Scott-B07421

> Sent: Tuesday, March 31, 2015 3:15 AM

> To: Medve Emilian-EMMEDVE1

> Cc: devicetree@vger.kernel.org; afleming@gmail.com; linuxppc-

> dev@lists.ozlabs.org; Liberman Igal-B31950

> Subject: Re: [PATCH 1/3] powerpc/mpc85xx: Add FMan clock nodes

> 

> On Tue, 2015-03-24 at 03:26 -0500, Emil Medve wrote:

> > Hello Scott,

> >

> >

> > On 03/23/2015 06:30 PM, Scott Wood wrote:

> > > On Thu, 2015-02-26 at 09:26 -0600, Emil Medve wrote:

> > >> From: Igal Liberman <Igal.Liberman@freescale.com>

> > >>

> > >> Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>

> > >> ---

> > >>  arch/powerpc/boot/dts/fsl/b4si-post.dtsi    | 11 +++++++++++

> > >>  arch/powerpc/boot/dts/fsl/p2041si-post.dtsi |  8 ++++++++

> > >> arch/powerpc/boot/dts/fsl/p3041si-post.dtsi |  8 ++++++++

> > >> arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 16 ++++++++++++++++

> > >> arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 13 +++++++++++++

> > >> arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 26

> > >> ++++++++++++++++++++++++++

> > >> arch/powerpc/boot/dts/fsl/t1040si-post.dtsi |  8 ++++++++

> > >> arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 11 +++++++++++

> > >> arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 20

> > >> ++++++++++++++++++++

> > >>  9 files changed, 121 insertions(+)

> > >>

> > >> diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi

> > >> b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi

> > >> index f8c325e..38621ef 100644

> > >> --- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi

> > >> +++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi

> > >> @@ -395,6 +395,17 @@

> > >>  		reg = <0xe0000 0xe00>;

> > >>  		fsl,has-rstcr;

> > >>  		fsl,liodn-bits = <12>;

> > >> +

> > >> +		fm0clk: fm0-clk-mux {

> > >> +			#clock-cells = <0>;

> > >> +			compatible = "fsl,fman-clk-mux";

> > >> +			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll0 3>,

> > >> +				 <&platform_pll 0>, <&pll1 1>, <&pll1 2>;

> > >> +			clock-names = "pll0", "pll0-div2", "pll0-div3",

> > >> +				      "pll0-div4", "platform-pll", "pll1-div2",

> > >> +				      "pll1-div3";

> > >> +			clock-output-names = "fm0-clk";

> > >> +		};

> > >

> > > Where's the binding for fsl,fman-clk-mux?

> > >

> >

> > Igal will follow-up with the binding document

> 

> Igal, ping?

> 

> I need a binding before I can apply the dts patch.

> 

> -Scott

> 


Hi Scott,
I'm working on FMan patches. I'll sent the binding ASAP. 

Thanks,
Igal
diff mbox

Patch

diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index f8c325e..38621ef 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -395,6 +395,17 @@ 
 		reg = <0xe0000 0xe00>;
 		fsl,has-rstcr;
 		fsl,liodn-bits = <12>;
+
+		fm0clk: fm0-clk-mux {
+			#clock-cells = <0>;
+			compatible = "fsl,fman-clk-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll0 3>,
+				 <&platform_pll 0>, <&pll1 1>, <&pll1 2>;
+			clock-names = "pll0", "pll0-div2", "pll0-div3",
+				      "pll0-div4", "platform-pll", "pll1-div2",
+				      "pll1-div3";
+			clock-output-names = "fm0-clk";
+		};
 	};
 
 /include/ "qoriq-clockgen2.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index 1f18b8b..60f63dc 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -316,6 +316,14 @@ 
 		fsl,has-rstcr;
 		#sleep-cells = <1>;
 		fsl,liodn-bits = <12>;
+
+		fm0clk: fm0-clk-mux {
+			#clock-cells = <0>;
+			compatible = "fsl,fman-clk-mux";
+			clocks = <&platform_pll 1>, <&pll1 1>;
+			clock-names = "platform-pll-div2", "pll1-div2";
+			clock-output-names = "fm0-clk";
+		};
 	};
 
 	pins: global-utilities@e0e00 {
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index a555d24..d4e6677 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -343,6 +343,14 @@ 
 		fsl,has-rstcr;
 		#sleep-cells = <1>;
 		fsl,liodn-bits = <12>;
+
+		fm0clk: fm0-clk-mux {
+			#clock-cells = <0>;
+			compatible = "fsl,fman-clk-mux";
+			clocks = <&platform_pll 1>, <&pll1 1>;
+			clock-names = "platform-pll-div2", "pll1-div2";
+			clock-output-names = "fm0-clk";
+		};
 	};
 
 	pins: global-utilities@e0e00 {
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 0fe7281..d1cb691 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -363,6 +363,22 @@ 
 		fsl,has-rstcr;
 		#sleep-cells = <1>;
 		fsl,liodn-bits = <12>;
+
+		fm0clk: fm0-clk-mux {
+			#clock-cells = <0>;
+			compatible = "fsl,fman-clk-mux";
+			clocks = <&platform_pll 1>, <&pll2 1>;
+			clock-names = "platform-pll-div2", "pll2-div2";
+			clock-output-names = "fm0-clk";
+		};
+
+		fm1clk: fm1-clk-mux {
+			#clock-cells = <0>;
+			compatible = "fsl,fman-clk-mux";
+			clocks = <&platform_pll 1>, <&pll2 1>;
+			clock-names = "platform-pll-div2", "pll2-div2";
+			clock-output-names = "fm1-clk";
+		};
 	};
 
 	pins: global-utilities@e0e00 {
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index a34ca20..9f3049d 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -348,6 +348,15 @@ 
 		fsl,has-rstcr;
 		#sleep-cells = <1>;
 		fsl,liodn-bits = <12>;
+
+		fm0clk: fm0-clk-mux {
+			#clock-cells = <0>;
+			compatible = "fsl,fman-clk-mux";
+			clocks = <&platform_pll 1>, <&pll1 1>, <&pll1 2>;
+			clock-names = "platform-pll-div2", "pll1-div2",
+				      "pll1-div4";
+			clock-output-names = "fm0-clk";
+		};
 	};
 
 	pins: global-utilities@e0e00 {
@@ -359,6 +368,10 @@ 
 /include/ "qoriq-clockgen1.dtsi"
 	global-utilities@e1000 {
 		compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
+
+		pll1: pll1@820 {
+			clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+		};
 	};
 
 	rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index bf57513..3dea4b6 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -308,6 +308,24 @@ 
 		fsl,has-rstcr;
 		#sleep-cells = <1>;
 		fsl,liodn-bits = <12>;
+
+		fm0clk: fm0-clk-mux {
+			#clock-cells = <0>;
+			compatible = "fsl,fman-clk-mux";
+			clocks = <&platform_pll 1>, <&pll2 1>, <&pll2 2>;
+			clock-names = "platform-pll-div2", "pll2-div2",
+				      "pll2-div4";
+			clock-output-names = "fm0-clk";
+		};
+
+		fm1clk: fm1-clk-mux {
+			#clock-cells = <0>;
+			compatible = "fsl,fman-clk-mux";
+			clocks = <&platform_pll 1>, <&pll2 1>, <&pll2 2>;
+			clock-names = "platform-pll-div2", "pll2-div2",
+				      "pll2-div4";
+			clock-output-names = "fm1-clk";
+		};
 	};
 
 	pins: global-utilities@e0e00 {
@@ -320,6 +338,14 @@ 
 	global-utilities@e1000 {
 		compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
 
+		pll2: pll2@840 {
+			#clock-cells = <1>;
+			reg = <0x840 0x4>;
+			compatible = "fsl,qoriq-core-pll-1.0";
+			clocks = <&sysclk>;
+			clock-output-names = "pll2", "pll2-div2", "pll2-div4";
+		};
+
 		mux2: mux2@40 {
 			#clock-cells = <0>;
 			reg = <0x40 0x4>;
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 4d41ce1..8f718c6 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -418,6 +418,14 @@ 
 		reg = <0xe0000 0xe00>;
 		fsl,has-rstcr;
 		fsl,liodn-bits = <12>;
+
+		fm0clk: fm0-clk-mux {
+			#clock-cells = <0>;
+			compatible = "fsl,fman-clk-mux";
+			clocks = <&platform_pll 0>;
+			clock-names = "platform-pll";
+			clock-output-names = "fm0-clk";
+		};
 	};
 
 /include/ "qoriq-clockgen2.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
index c2cb0f3..06e76ec 100644
--- a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -530,6 +530,17 @@ 
 		reg = <0xe0000 0xe00>;
 		fsl,has-rstcr;
 		fsl,liodn-bits = <12>;
+
+		fm0clk: fm0-clk-mux {
+			#clock-cells = <0>;
+			compatible = "fsl,fman-clk-mux";
+			clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll0 3>,
+				 <&platform_pll 0>, <&pll1 1>, <&pll1 2>;
+			clock-names = "pll0", "pll0-div2", "pll0-div3",
+				      "pll0-div4", "platform-pll", "pll1-div2",
+				      "pll1-div3";
+			clock-output-names = "fm0-clk";
+		};
 	};
 
 /include/ "qoriq-clockgen2.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index c18245e..5ef5ff0 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -945,6 +945,26 @@ 
 		reg = <0xe0000 0xe00>;
 		fsl,has-rstcr;
 		fsl,liodn-bits = <12>;
+
+		fm0clk: fm0-clk-mux {
+			#clock-cells = <0>;
+			compatible = "fsl,fman-clk-mux";
+			clocks = <&pll0 1>, <&pll0 2>, <&pll0 3>,
+				 <&platform_pll 0>, <&pll1 1>;
+			clock-names = "pll0-div2", "pll0-div3", "pll0-div4",
+				      "platform-pll", "pll1-div2";
+			clock-output-names = "fm0-clk";
+		};
+
+		fm1clk: fm1-clk-mux {
+			#clock-cells = <0>;
+			compatible = "fsl,fman-clk-mux";
+			clocks = <&pll1 1>, <&pll1 2>, <&pll1 3>,
+				 <&platform_pll 0>, <&pll0 1>, <&pll0 2>;
+			clock-names = "pll1-div2", "pll1-div3", "pll1-div4",
+				      "platform-pll", "pll0-div2", "pll0-div3";
+			clock-output-names = "fm1-clk";
+		};
 	};
 
 /include/ "qoriq-clockgen2.dtsi"