From patchwork Thu Jul 17 11:22:24 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mihai Caraman X-Patchwork-Id: 371078 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5C6AE14010C for ; Thu, 17 Jul 2014 21:24:28 +1000 (EST) Received: from ozlabs.org (ozlabs.org [103.22.144.67]) by lists.ozlabs.org (Postfix) with ESMTP id 3C11E1A0866 for ; Thu, 17 Jul 2014 21:24:28 +1000 (EST) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from na01-bn1-obe.outbound.protection.outlook.com (dns-bn1lp0143.outbound.protection.outlook.com [207.46.163.143]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 9AA231A0019 for ; Thu, 17 Jul 2014 21:22:43 +1000 (EST) Received: from BN3PR0301CA0019.namprd03.prod.outlook.com (25.160.180.157) by DM2PR03MB512.namprd03.prod.outlook.com (10.141.87.22) with Microsoft SMTP Server (TLS) id 15.0.974.11; Thu, 17 Jul 2014 11:22:36 +0000 Received: from BL2FFO11FD059.protection.gbl (2a01:111:f400:7c09::151) by BN3PR0301CA0019.outlook.office365.com (2a01:111:e400:4000::29) with Microsoft SMTP Server (TLS) id 15.0.990.7 via Frontend Transport; Thu, 17 Jul 2014 11:22:35 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BL2FFO11FD059.mail.protection.outlook.com (10.173.161.187) with Microsoft SMTP Server (TLS) id 15.0.980.11 via Frontend Transport; Thu, 17 Jul 2014 11:22:35 +0000 Received: from fsr-fed1764-012.ea.freescale.net (fsr-fed1764-012-010171073213.ea.freescale.net [10.171.73.213]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s6HBMVit014734; Thu, 17 Jul 2014 04:22:33 -0700 From: Mihai Caraman To: Subject: [PATCH v5 1/5] KVM: PPC: e500mc: Revert "add load inst fixup" Date: Thu, 17 Jul 2014 14:22:24 +0300 Message-ID: <1405596148-1507-2-git-send-email-mihai.caraman@freescale.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1405596148-1507-1-git-send-email-mihai.caraman@freescale.com> References: <1405596148-1507-1-git-send-email-mihai.caraman@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(189002)(199002)(83072002)(97736001)(88136002)(20776003)(89996001)(46102001)(107046002)(19580405001)(104016003)(85852003)(76482001)(31966008)(110136001)(87286001)(50986999)(83322001)(81342001)(4396001)(105606002)(95666004)(92726001)(47776003)(104166001)(84676001)(6806004)(99396002)(76176999)(86362001)(26826002)(36756003)(48376002)(44976005)(229853001)(79102001)(106466001)(19580395003)(77156001)(93916002)(102836001)(85306003)(80022001)(64706001)(68736004)(74502001)(81542001)(77982001)(50466002)(50226001)(2351001)(92566001)(21056001)(33646002)(74662001)(62966002)(87936001); DIR:OUT; SFP:; SCL:1; SRVR:DM2PR03MB512; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-Forefront-PRVS: 027578BB13 Received-SPF: Fail (: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=mihai.caraman@freescale.com; X-OriginatorOrg: freescale.com Cc: Mihai Caraman , linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" The commit 1d628af7 "add load inst fixup" made an attempt to handle failures generated by reading the guest current instruction. The fixup code that was added works by chance hiding the real issue. Load external pid (lwepx) instruction, used by KVM to read guest instructions, is executed in a subsituted guest translation context (EPLC[EGS] = 1). In consequence lwepx's TLB error and data storage interrupts need to be handled by KVM, even though these interrupts are generated from host context (MSR[GS] = 0) where lwepx is executed. Currently, KVM hooks only interrupts generated from guest context (MSR[GS] = 1), doing minimal checks on the fast path to avoid host performance degradation. As a result, the host kernel handles lwepx faults searching the faulting guest data address (loaded in DEAR) in its own Logical Partition ID (LPID) 0 context. In case a host translation is found the execution returns to the lwepx instruction instead of the fixup, the host ending up in an infinite loop. Revert the commit "add load inst fixup". lwepx issue will be addressed in a subsequent patch without needing fixup code. Signed-off-by: Mihai Caraman --- v5-v2: - no change arch/powerpc/kvm/bookehv_interrupts.S | 26 +------------------------- 1 file changed, 1 insertion(+), 25 deletions(-) diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S index a1712b8..6ff4480 100644 --- a/arch/powerpc/kvm/bookehv_interrupts.S +++ b/arch/powerpc/kvm/bookehv_interrupts.S @@ -29,7 +29,6 @@ #include #include #include -#include #ifdef CONFIG_64BIT #include @@ -164,32 +163,9 @@ PPC_STL r30, VCPU_GPR(R30)(r4) PPC_STL r31, VCPU_GPR(R31)(r4) mtspr SPRN_EPLC, r8 - - /* disable preemption, so we are sure we hit the fixup handler */ - CURRENT_THREAD_INFO(r8, r1) - li r7, 1 - stw r7, TI_PREEMPT(r8) - isync - - /* - * In case the read goes wrong, we catch it and write an invalid value - * in LAST_INST instead. - */ -1: lwepx r9, 0, r5 -2: -.section .fixup, "ax" -3: li r9, KVM_INST_FETCH_FAILED - b 2b -.previous -.section __ex_table,"a" - PPC_LONG_ALIGN - PPC_LONG 1b,3b -.previous - + lwepx r9, 0, r5 mtspr SPRN_EPLC, r3 - li r7, 0 - stw r7, TI_PREEMPT(r8) stw r9, VCPU_LAST_INST(r4) .endif