| Message ID | 1394612762-36308-1-git-send-email-B45475@freescale.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Scott Wood |
| Headers | show |
On Wed, 2014-03-12 at 16:26 +0800, Zhao Qiang wrote: > Signed-off-by: Zhao Qiang <B45475@freescale.com> > --- > arch/powerpc/boot/dts/t1040rdb.dts | 43 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > > diff --git a/arch/powerpc/boot/dts/t1040rdb.dts b/arch/powerpc/boot/dts/t1040rdb.dts > index e2eee18..6ff0412 100644 > --- a/arch/powerpc/boot/dts/t1040rdb.dts > +++ b/arch/powerpc/boot/dts/t1040rdb.dts > @@ -268,6 +268,49 @@ > fsl,fman-mac = <&enet4>; > }; > }; > + > + qe: qe@ffe139999 { > + ranges = <0x0 0xf 0xfe140000 0x40000>; > + reg = <0xf 0xfe140000 0 0x480>; reg does not match unit address Missing compatible > + si1: si@700 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,qe-si"; > + reg = <0x700 0x80>; > + }; Missing binding > + > + siram1: siram@1000 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "fsl,qe-siram"; > + reg = <0x1000 0x800>; > + }; Missing binding > + > + tdma: ucc@2000 { > + compatible = "fsl,ucc-tdm"; > + rx-clock-name = "clk3"; > + tx-clock-name = "clk4"; > + fsl,rx-sync-clock = "rsync_pin"; > + fsl,tx-sync-clock = "tsync_pin"; > + fsl,tx-timeslot = <0xfffffffe>; > + fsl,rx-timeslot = <0xfffffffe>; > + fsl,tdm-framer-type = "e1"; > + fsl,tdm-mode = "normal"; > + fsl,tdm-id = <0>; > + fsl,siram-entry-id = <0>; > + }; Missing binding > + serial: ucc@2200 { > + device_type = "serial"; > + compatible = "ucc_uart"; > + port-number = <1>; > + rx-clock-name = "brg2"; > + tx-clock-name = "brg2"; > + }; Missing binding -Scott
On Wed, 2014-03-12 at 16:26 +0800, Zhao Qiang wrote: > Signed-off-by: Zhao Qiang <B45475@freescale.com> > --- > arch/powerpc/boot/dts/t1040rdb.dts | 43 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 43 insertions(+) Presumably this is on top of this patch: http://patchwork.ozlabs.org/patch/314138/ ...since there's no existing t1040 device tree support. Always mention when your patch is on top of a patch that hasn't yet been merged and isn't in the same patch set. At least some of this stuff seems like it should be in t1040si-post.dts (or a file included by it), rather than the board dts. > + tdma: ucc@2000 { > + compatible = "fsl,ucc-tdm"; > + rx-clock-name = "clk3"; > + tx-clock-name = "clk4"; > + fsl,rx-sync-clock = "rsync_pin"; > + fsl,tx-sync-clock = "tsync_pin"; > + fsl,tx-timeslot = <0xfffffffe>; > + fsl,rx-timeslot = <0xfffffffe>; > + fsl,tdm-framer-type = "e1"; > + fsl,tdm-mode = "normal"; > + fsl,tdm-id = <0>; > + fsl,siram-entry-id = <0>; > + }; > + > + serial: ucc@2200 { > + device_type = "serial"; > + compatible = "ucc_uart"; > + port-number = <1>; > + rx-clock-name = "brg2"; > + tx-clock-name = "brg2"; > + }; Missing reg. -Scott
On Wed, 2014-03-13 at 2:46 AM, Scott wrote: > -----Original Message----- > From: Wood Scott-B07421 > Sent: Thursday, March 13, 2014 2:46 AM > To: Zhao Qiang-B45475 > Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Xie Xiaobo-R63061 > Subject: Re: [PATCH] T1040RDB: add qe node for T1040RDB dts > > On Wed, 2014-03-12 at 16:26 +0800, Zhao Qiang wrote: > > Signed-off-by: Zhao Qiang <B45475@freescale.com> > > --- > > arch/powerpc/boot/dts/t1040rdb.dts | 43 > > ++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 43 insertions(+) > > Presumably this is on top of this patch: > http://patchwork.ozlabs.org/patch/314138/ > > ...since there's no existing t1040 device tree support. Always mention > when your patch is on top of a patch that hasn't yet been merged and > isn't in the same patch set. > > At least some of this stuff seems like it should be in t1040si-post.dts > (or a file included by it), rather than the board dts. Every board can use ucc differently, It is not correct to put this node into t1040si-post.dtsi. For example t1040qds can use ucc1 to tdm while maybe t1040rdb use ucc1 to uart. > > > + tdma: ucc@2000 { > > + compatible = "fsl,ucc-tdm"; > > + rx-clock-name = "clk3"; > > + tx-clock-name = "clk4"; > > + fsl,rx-sync-clock = "rsync_pin"; > > + fsl,tx-sync-clock = "tsync_pin"; > > + fsl,tx-timeslot = <0xfffffffe>; > > + fsl,rx-timeslot = <0xfffffffe>; > > + fsl,tdm-framer-type = "e1"; > > + fsl,tdm-mode = "normal"; > > + fsl,tdm-id = <0>; > > + fsl,siram-entry-id = <0>; > > + }; > > + > > + serial: ucc@2200 { > > + device_type = "serial"; > > + compatible = "ucc_uart"; > > + port-number = <1>; > > + rx-clock-name = "brg2"; > > + tx-clock-name = "brg2"; > > + }; > > Missing reg. > > -Scott >
On Wed, 2014-03-12 at 20:56 -0500, Zhao Qiang-B45475 wrote: > On Wed, 2014-03-13 at 2:46 AM, Scott wrote: > > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Thursday, March 13, 2014 2:46 AM > > To: Zhao Qiang-B45475 > > Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Xie Xiaobo-R63061 > > Subject: Re: [PATCH] T1040RDB: add qe node for T1040RDB dts > > > > On Wed, 2014-03-12 at 16:26 +0800, Zhao Qiang wrote: > > > Signed-off-by: Zhao Qiang <B45475@freescale.com> > > > --- > > > arch/powerpc/boot/dts/t1040rdb.dts | 43 > > > ++++++++++++++++++++++++++++++++++++++ > > > 1 file changed, 43 insertions(+) > > > > Presumably this is on top of this patch: > > http://patchwork.ozlabs.org/patch/314138/ > > > > ...since there's no existing t1040 device tree support. Always mention > > when your patch is on top of a patch that hasn't yet been merged and > > isn't in the same patch set. > > > > At least some of this stuff seems like it should be in t1040si-post.dts > > (or a file included by it), rather than the board dts. > > Every board can use ucc differently, It is not correct to put this node into t1040si-post.dtsi. > For example t1040qds can use ucc1 to tdm while maybe t1040rdb use ucc1 to uart. That's why I said "some". :-) Anything that is specific to the board should be in the board file, but it's not clear that everything in this patch is board-specific. si/siram? Reg/ranges on the qe node? Etc. -Scott
diff --git a/arch/powerpc/boot/dts/t1040rdb.dts b/arch/powerpc/boot/dts/t1040rdb.dts index e2eee18..6ff0412 100644 --- a/arch/powerpc/boot/dts/t1040rdb.dts +++ b/arch/powerpc/boot/dts/t1040rdb.dts @@ -268,6 +268,49 @@ fsl,fman-mac = <&enet4>; }; }; + + qe: qe@ffe139999 { + ranges = <0x0 0xf 0xfe140000 0x40000>; + reg = <0xf 0xfe140000 0 0x480>; + brg-frequency = <0>; + bus-frequency = <0>; + + si1: si@700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,qe-si"; + reg = <0x700 0x80>; + }; + + siram1: siram@1000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-siram"; + reg = <0x1000 0x800>; + }; + + tdma: ucc@2000 { + compatible = "fsl,ucc-tdm"; + rx-clock-name = "clk3"; + tx-clock-name = "clk4"; + fsl,rx-sync-clock = "rsync_pin"; + fsl,tx-sync-clock = "tsync_pin"; + fsl,tx-timeslot = <0xfffffffe>; + fsl,rx-timeslot = <0xfffffffe>; + fsl,tdm-framer-type = "e1"; + fsl,tdm-mode = "normal"; + fsl,tdm-id = <0>; + fsl,siram-entry-id = <0>; + }; + + serial: ucc@2200 { + device_type = "serial"; + compatible = "ucc_uart"; + port-number = <1>; + rx-clock-name = "brg2"; + tx-clock-name = "brg2"; + }; + }; }; /include/ "fsl/t1040si-post.dtsi" /include/ "fsl/qoriq-dpaa-res3.dtsi"
Signed-off-by: Zhao Qiang <B45475@freescale.com> --- arch/powerpc/boot/dts/t1040rdb.dts | 43 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+)