| Message ID | 1386153162-11225-5-git-send-email-khandual@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
On Wed, Dec 04, 2013 at 04:02:36PM +0530, Anshuman Khandual wrote: > This patch adds conditional branch filtering support, > enabling it for PERF_SAMPLE_BRANCH_COND in perf branch > stack sampling framework by utilizing an available > software filter X86_BR_JCC. Newer Intel CPUs a hardware filter too for "not a conditional branch". I can look at implementing that. The software option seems fine for now. -Andi > > Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com> > Reviewed-by: Stephane Eranian <eranian@google.com> > --- > arch/x86/kernel/cpu/perf_event_intel_lbr.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c > index d82d155..9dd2459 100644 > --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c > +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c > @@ -384,6 +384,9 @@ static void intel_pmu_setup_sw_lbr_filter(struct perf_event *event) > if (br_type & PERF_SAMPLE_BRANCH_NO_TX) > mask |= X86_BR_NO_TX; > > + if (br_type & PERF_SAMPLE_BRANCH_COND) > + mask |= X86_BR_JCC; > + > /* > * stash actual user request into reg, it may > * be used by fixup code for some CPU > @@ -678,6 +681,7 @@ static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = { > * NHM/WSM erratum: must include IND_JMP to capture IND_CALL > */ > [PERF_SAMPLE_BRANCH_IND_CALL] = LBR_IND_CALL | LBR_IND_JMP, > + [PERF_SAMPLE_BRANCH_COND] = LBR_JCC, > }; > > static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = { > @@ -689,6 +693,7 @@ static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = { > [PERF_SAMPLE_BRANCH_ANY_CALL] = LBR_REL_CALL | LBR_IND_CALL > | LBR_FAR, > [PERF_SAMPLE_BRANCH_IND_CALL] = LBR_IND_CALL, > + [PERF_SAMPLE_BRANCH_COND] = LBR_JCC, > }; > > /* core */ > -- > 1.7.11.7 >
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c index d82d155..9dd2459 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c @@ -384,6 +384,9 @@ static void intel_pmu_setup_sw_lbr_filter(struct perf_event *event) if (br_type & PERF_SAMPLE_BRANCH_NO_TX) mask |= X86_BR_NO_TX; + if (br_type & PERF_SAMPLE_BRANCH_COND) + mask |= X86_BR_JCC; + /* * stash actual user request into reg, it may * be used by fixup code for some CPU @@ -678,6 +681,7 @@ static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = { * NHM/WSM erratum: must include IND_JMP to capture IND_CALL */ [PERF_SAMPLE_BRANCH_IND_CALL] = LBR_IND_CALL | LBR_IND_JMP, + [PERF_SAMPLE_BRANCH_COND] = LBR_JCC, }; static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = { @@ -689,6 +693,7 @@ static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = { [PERF_SAMPLE_BRANCH_ANY_CALL] = LBR_REL_CALL | LBR_IND_CALL | LBR_FAR, [PERF_SAMPLE_BRANCH_IND_CALL] = LBR_IND_CALL, + [PERF_SAMPLE_BRANCH_COND] = LBR_JCC, }; /* core */