From patchwork Mon Jul 16 02:45:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hongtao Jia X-Patchwork-Id: 171119 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id A235C2C0281 for ; Mon, 16 Jul 2012 13:07:59 +1000 (EST) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe002.messaging.microsoft.com [216.32.181.182]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 4FE812C00E1 for ; Mon, 16 Jul 2012 13:07:32 +1000 (EST) Received: from mail213-ch1-R.bigfish.com (10.43.68.247) by CH1EHSOBE001.bigfish.com (10.43.70.51) with Microsoft SMTP Server id 14.1.225.23; Mon, 16 Jul 2012 03:07:26 +0000 Received: from mail213-ch1 (localhost [127.0.0.1]) by mail213-ch1-R.bigfish.com (Postfix) with ESMTP id 0B8B12E03D3; Mon, 16 Jul 2012 03:07:26 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839he5bhf0ah107ah) Received: from mail213-ch1 (localhost.localdomain [127.0.0.1]) by mail213-ch1 (MessageSwitch) id 1342408043588185_28393; Mon, 16 Jul 2012 03:07:23 +0000 (UTC) Received: from CH1EHSMHS017.bigfish.com (snatpool2.int.messaging.microsoft.com [10.43.68.235]) by mail213-ch1.bigfish.com (Postfix) with ESMTP id 8D893801DA; Mon, 16 Jul 2012 03:07:23 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS017.bigfish.com (10.43.70.17) with Microsoft SMTP Server (TLS) id 14.1.225.23; Mon, 16 Jul 2012 03:07:23 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.2.298.5; Sun, 15 Jul 2012 22:07:23 -0500 Received: from rock.am.freescale.net (rock.ap.freescale.net [10.193.20.106]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id q6G37JoO028277; Sun, 15 Jul 2012 20:07:20 -0700 From: Jia Hongtao To: , Subject: [PATCH V3] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx Date: Mon, 16 Jul 2012 10:45:50 +0800 Message-ID: <1342406750-32694-1-git-send-email-B38951@freescale.com> X-Mailer: git-send-email 1.7.5.1 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: b38951@freescale.com X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe goes down. when the link goes down, Non-posted transactions issued via the ATMU requiring completion result in an instruction stall. At the same time a machine-check exception is generated to the core to allow further processing by the handler. We implements the handler which skips the instruction caused the stall. Signed-off-by: Zhao Chenhui Signed-off-by: Li Yang Signed-off-by: Liu Shuo Signed-off-by: Jia Hongtao --- V3 changed: Just rebase the patch. arch/powerpc/kernel/cpu_setup_fsl_booke.S | 2 +- arch/powerpc/kernel/traps.c | 3 ++ arch/powerpc/sysdev/fsl_pci.c | 39 +++++++++++++++++++++++++++++ arch/powerpc/sysdev/fsl_pci.h | 6 ++++ 4 files changed, 49 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index 69fdd23..9c4b768 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -64,7 +64,7 @@ _GLOBAL(__setup_cpu_e500v2) bl __e500_icache_setup bl __e500_dcache_setup bl __setup_e500_ivors -#ifdef CONFIG_FSL_RIO +#if defined(CONFIG_FSL_RIO) || defined(CONFIG_FSL_PCI) /* Ensure that RFXE is set */ mfspr r3,SPRN_HID1 oris r3,r3,HID1_RFXE@h diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index 1589723..096a1a1 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -59,6 +59,7 @@ #include #include #include +#include #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) int (*__debugger)(struct pt_regs *regs) __read_mostly; @@ -555,6 +556,8 @@ int machine_check_e500(struct pt_regs *regs) if (reason & MCSR_BUS_RBERR) { if (fsl_rio_mcheck_exception(regs)) return 1; + if (fsl_pci_mcheck_exception(regs)) + return 1; } printk("Machine check in kernel mode.\n"); diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index a7b2a60..52f3b5d 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -808,6 +809,44 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose) return 0; } +static int is_in_pci_mem_space(phys_addr_t addr) +{ + struct pci_controller *hose; + struct resource *res; + int i; + + list_for_each_entry(hose, &hose_list, list_node) { + if (!early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) + continue; + + for (i = 0; i < 3; i++) { + res = &hose->mem_resources[i]; + if ((res->flags & IORESOURCE_MEM) && + addr >= res->start && addr <= res->end) + return 1; + } + } + return 0; +} + +int fsl_pci_mcheck_exception(struct pt_regs *regs) +{ + phys_addr_t addr = 0; + +#ifdef CONFIG_PHYS_64BIT + addr = mfspr(SPRN_MCARU); + addr <<= 32; +#endif + addr += mfspr(SPRN_MCAR); + + if (is_in_pci_mem_space(addr)) { + regs->nip += 4; + return 1; + } + + return 0; +} + #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) static const struct of_device_id pci_ids[] = { { .compatible = "fsl,mpc8540-pci", }, diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index baa0fd1..efd1907 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -101,5 +101,11 @@ void fsl_pci_init(void); static inline void fsl_pci_init(void) {} #endif +#ifdef CONFIG_FSL_PCI +extern int fsl_pci_mcheck_exception(struct pt_regs *); +#else +static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; } +#endif + #endif /* __POWERPC_FSL_PCI_H */ #endif /* __KERNEL__ */