From patchwork Fri Nov 18 17:50:00 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timur Tabi X-Patchwork-Id: 126458 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 9746DB756C for ; Sat, 19 Nov 2011 04:50:17 +1100 (EST) Received: by ozlabs.org (Postfix) id 7E54FB722D; Sat, 19 Nov 2011 04:50:09 +1100 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: from TX2EHSOBE001.bigfish.com (tx2ehsobe001.messaging.microsoft.com [65.55.88.11]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id ED908B7230 for ; Sat, 19 Nov 2011 04:50:08 +1100 (EST) Received: from mail47-tx2-R.bigfish.com (10.9.14.250) by TX2EHSOBE001.bigfish.com (10.9.40.21) with Microsoft SMTP Server id 14.1.225.22; Fri, 18 Nov 2011 17:49:30 +0000 Received: from mail47-tx2 (localhost.localdomain [127.0.0.1]) by mail47-tx2-R.bigfish.com (Postfix) with ESMTP id 83E7C1A100C2 for ; Fri, 18 Nov 2011 17:49:51 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail47-tx2 (localhost.localdomain [127.0.0.1]) by mail47-tx2 (MessageSwitch) id 1321638591374399_12730; Fri, 18 Nov 2011 17:49:51 +0000 (UTC) Received: from TX2EHSMHS047.bigfish.com (unknown [10.9.14.246]) by mail47-tx2.bigfish.com (Postfix) with ESMTP id 52387660053 for ; Fri, 18 Nov 2011 17:49:51 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS047.bigfish.com (10.9.99.147) with Microsoft SMTP Server (TLS) id 14.1.225.22; Fri, 18 Nov 2011 17:51:05 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.339.2; Fri, 18 Nov 2011 11:50:02 -0600 Received: from efes.am.freescale.net (efes.am.freescale.net [10.82.123.3]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id pAIHo194002693; Fri, 18 Nov 2011 11:50:02 -0600 (CST) From: Timur Tabi To: , , Subject: [PATCH 2/3] powerpc/85xx: add pixis indirect mode device tree node Date: Fri, 18 Nov 2011 11:50:00 -0600 Message-ID: <1321638601-6861-2-git-send-email-timur@freescale.com> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1321638601-6861-1-git-send-email-timur@freescale.com> References: <1321638601-6861-1-git-send-email-timur@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org The Freescale P1022 has a unique pin muxing "feature" where the DIU video controller's video signals are muxed with 24 of the local bus address signals. When the DIU is enabled, the bulk of the local bus is disabled, preventing access to memory-mapped devices like NOR flash and the pixis FPGA. In this situation, the pixis supports "indirect mode", which allows access to the pixis itself by reading/writing addresses on specific local bus chip selects. CS0 is used to select which pixis register to access, and CS1 is used to read/write the value. To support this, we introduce another board-control child node of the localbus node that contains a 'reg' property for CS0 and CS1. This will produce the correct physical addresses for CS0 and CS1. Signed-off-by: Timur Tabi --- arch/powerpc/boot/dts/p1022ds.dts | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts index 24a73e9..3e85d8c 100644 --- a/arch/powerpc/boot/dts/p1022ds.dts +++ b/arch/powerpc/boot/dts/p1022ds.dts @@ -24,6 +24,20 @@ 0x2 0x0 0xf 0xffa00000 0x00040000 0x3 0x0 0xf 0xffdf0000 0x00008000>; + /* + * This node is used to access the pixis via "indirect" mode, + * which is done by writing the pixis register index to chip + * select 0 and the value to/from chip select 1. Indirect + * mode is the only way to access the pixis when DIU video + * is enabled. Note that this assumes that the first column + * of the 'ranges' property above is the chip select number. + */ + board-control@0,0 { + compatible = "fsl,p1022ds-indirect-pixis"; + reg = <0x0 0x0 1 /* CS0 */ + 0x1 0x0 1>; /* CS1 */ + }; + nor@0,0 { #address-cells = <1>; #size-cells = <1>;