From patchwork Thu Feb 3 01:51:39 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Meador Inge X-Patchwork-Id: 81606 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from bilbo.ozlabs.org (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 19D55B74B0 for ; Thu, 3 Feb 2011 12:52:22 +1100 (EST) Received: from relay1.mentorg.com (relay1.mentorg.com [192.94.38.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "relay1.mentorg.com", Issuer "Entrust Certification Authority - L1B" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 1392BB7113; Thu, 3 Feb 2011 12:51:49 +1100 (EST) Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1PkoMM-0002I0-Es from meador_inge@mentor.com ; Wed, 02 Feb 2011 17:51:46 -0800 Received: from na2-mail.mgc.mentorg.com ([134.86.114.213]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Wed, 2 Feb 2011 17:51:45 -0800 Received: from localhost.localdomain ([172.30.88.225]) by na2-mail.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 2 Feb 2011 18:51:44 -0700 From: Meador Inge To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH v2 2/3] powerpc: document the Open PIC device tree binding Date: Wed, 2 Feb 2011 19:51:39 -0600 Message-Id: <1296697900-14004-3-git-send-email-meador_inge@mentor.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1296697900-14004-1-git-send-email-meador_inge@mentor.com> References: <1296697900-14004-1-git-send-email-meador_inge@mentor.com> X-OriginalArrivalTime: 03 Feb 2011 01:51:44.0955 (UTC) FILETIME=[E94D70B0:01CBC344] Cc: devicetree-discuss@lists.ozlabs.org, Hollis Blanchard , Stuart Yoder X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org This binding documents several properties that have been in use for quite some time, and adds one new property 'no-reset', which controls whether the Open PIC should be reset during runtime initialization. The general formatting and interrupt specifier definition is based off of Stuart Yoder's FSL MPIC binding. Signed-off-by: Meador Inge CC: Hollis Blanchard CC: Stuart Yoder --- Documentation/powerpc/dts-bindings/open-pic.txt | 115 +++++++++++++++++++++++ 1 files changed, 115 insertions(+), 0 deletions(-) create mode 100644 Documentation/powerpc/dts-bindings/open-pic.txt diff --git a/Documentation/powerpc/dts-bindings/open-pic.txt b/Documentation/powerpc/dts-bindings/open-pic.txt new file mode 100644 index 0000000..447ef65 --- /dev/null +++ b/Documentation/powerpc/dts-bindings/open-pic.txt @@ -0,0 +1,115 @@ +* Open PIC Binding + +This binding specifies what properties must be available in the device tree +representation of an Open PIC compliant interrupt controller. This binding is +based on the binding defined for Open PIC in [1] and is a superset of that +binding. + +PROPERTIES + + NOTE: Many of these descriptions were paraphrased here from [1] to aid + readability. + + - compatible + Usage: required + Value type: + Definition: Specifies the compatibility list for the PIC. The + property value shall include "open-pic". + + - reg + Usage: required + Value type: + Definition: Specifies the base physical address(s) and size(s) of this + PIC's addressable register space. + + - interrupt-controller + Usage: required + Value type: + Definition: The presence of this property identifies the node + as an Open PIC. No property value should be defined. + + - #interrupt-cells + Usage: required + Value type: + Definition: Specifies the number of cells needed to encode an + interrupt source. Shall be 2. + + - #address-cells + Usage: required + Value type: + Definition: Specifies the number of cells needed to encode an + address. The value of this property shall always be 0. + As such, 'interrupt-map' nodes do not have to specify a + parent unit address. + + - no-reset + Usage: optional + Value type: + Definition: The presence of this property indicates that the PIC + should not be reset during runtime initialization. The presence of + this property also mandates that any initialization related to + interrupt sources shall be limited to sources explicitly referenced + in the device tree. + +INTERRUPT SPECIFIER DEFINITION + + Interrupt specifiers consists of 2 cells encoded as + follows: + + <1st-cell> interrupt-number + + Identifies the interrupt source. + + <2nd-cell> level-sense information, encoded as follows: + 0 = low-to-high edge triggered + 1 = active low level-sensitive + 2 = active high level-sensitive + 3 = high-to-low edge triggered + +EXAMPLE 1 + + /* + * An Open PIC interrupt controller + */ + mpic: pic@40000 { + // This is an interrupt controller node. + interrupt-controller; + + // No address cells so that 'interrupt-map' nodes which reference + // this Open PIC node do not need a parent address specifier. + #address-cells = <0>; + + // Two cells to encode interrupt sources. + #interrupt-cells = <2>; + + // Offset address of 0x40000 and size of 0x40000. + reg = <0x40000 0x40000>; + + // Compatible with Open PIC. + compatible = "open-pic"; + + // The PIC should not be reset. + no-reset; + }; + +EXAMPLE 2 + + /* + * An interrupt generating device that is wired to an Open PIC. + */ + serial0: serial@4500 { + // Interrupt source '42' that is active high level-sensitive. + // Note that there are only two cells as specified in the interrupt + // parent's '#interrupt-cells' property. + interrupts = <42 2>; + + // The interrupt controller that this device is wired to. + interrupt-parent = <&mpic>; + }; + +REFERENCES + +[1] Power.org (TM) Standard for Embedded Power Architecture (TM) Platform + Requirements (ePAPR), Version 1.0, July 2008. + (http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf) +