From patchwork Wed Jun 8 08:51:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 632047 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rPj8R4KXSz9t0t for ; Wed, 8 Jun 2016 19:00:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161659AbcFHJAy (ORCPT ); Wed, 8 Jun 2016 05:00:54 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:18361 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1161899AbcFHJAe (ORCPT ); Wed, 8 Jun 2016 05:00:34 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Wed, 08 Jun 2016 02:00:22 -0700 Received: from HQMAIL104.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Wed, 08 Jun 2016 01:57:24 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 08 Jun 2016 01:57:24 -0700 Received: from UKMAIL102.nvidia.com (10.26.138.15) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 8 Jun 2016 09:00:32 +0000 Received: from [10.21.132.106] (10.21.132.106) by UKMAIL102.nvidia.com (10.26.138.15) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 8 Jun 2016 09:00:28 +0000 Subject: Re: [PATCH 7/8] dmaengine: tegra20-apb-dma: Only calculate residue if txstate exists. To: Peter Griffin , , , , , , , , , , , , , , , References: <1465321121-22238-1-git-send-email-peter.griffin@linaro.org> <1465321121-22238-8-git-send-email-peter.griffin@linaro.org> CC: , , , From: Jon Hunter Message-ID: <5757DCAD.1090106@nvidia.com> Date: Wed, 8 Jun 2016 09:51:57 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 In-Reply-To: <1465321121-22238-8-git-send-email-peter.griffin@linaro.org> X-Originating-IP: [10.21.132.106] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL102.nvidia.com (10.26.138.15) Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Hi Peter, On 07/06/16 18:38, Peter Griffin wrote: > There is no point calculating the residue if there is > no txstate to store the value. > > Signed-off-by: Peter Griffin > --- > drivers/dma/tegra20-apb-dma.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c > index 01e316f..7f4af8c 100644 > --- a/drivers/dma/tegra20-apb-dma.c > +++ b/drivers/dma/tegra20-apb-dma.c > @@ -814,7 +814,7 @@ static enum dma_status tegra_dma_tx_status(struct dma_chan *dc, > unsigned int residual; > > ret = dma_cookie_status(dc, cookie, txstate); > - if (ret == DMA_COMPLETE) > + if (ret == DMA_COMPLETE || !txstate) > return ret; Thanks for reporting this. I agree that we should not do this, however, looking at the code for Tegra, I am wondering if this could change the actual state that is returned. Looking at dma_cookie_status() it will call dma_async_is_complete() which will return either DMA_COMPLETE or DMA_IN_PROGRESS. It could be possible that the actual state for the DMA transfer in the tegra driver is DMA_ERROR, so I am wondering if we should do something like the following ... Cheers Jon diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c index 01e316f73559..45edab7418d0 100644 --- a/drivers/dma/tegra20-apb-dma.c +++ b/drivers/dma/tegra20-apb-dma.c @@ -822,13 +822,8 @@ static enum dma_status tegra_dma_tx_status(struct dma_chan *dc, /* Check on wait_ack desc status */ list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) { if (dma_desc->txd.cookie == cookie) { - residual = dma_desc->bytes_requested - - (dma_desc->bytes_transferred % - dma_desc->bytes_requested); - dma_set_residue(txstate, residual); ret = dma_desc->dma_status; - spin_unlock_irqrestore(&tdc->lock, flags); - return ret; + goto found; } } @@ -836,17 +831,23 @@ static enum dma_status tegra_dma_tx_status(struct dma_chan *dc, list_for_each_entry(sg_req, &tdc->pending_sg_req, node) { dma_desc = sg_req->dma_desc; if (dma_desc->txd.cookie == cookie) { - residual = dma_desc->bytes_requested - - (dma_desc->bytes_transferred % - dma_desc->bytes_requested); - dma_set_residue(txstate, residual); ret = dma_desc->dma_status; - spin_unlock_irqrestore(&tdc->lock, flags); - return ret; + goto found; } } - dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie); + dev_warn(tdc2dev(tdc), "cookie %d not found\n", cookie); + spin_unlock_irqrestore(&tdc->lock, flags); + return ret; + +found: + if (txstate) { + residual = dma_desc->bytes_requested - + (dma_desc->bytes_transferred % + dma_desc->bytes_requested); + dma_set_residue(txstate, residual); + } + spin_unlock_irqrestore(&tdc->lock, flags); return ret; }