@@ -349,6 +349,21 @@ scm: scm {
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
};
+ cpucp_scmi {
+ compatible = "arm,scmi";
+ mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>;
+
+ mbox-names = "tx", "rx";
+ shmem = <&cpucp_scp_lpri0>, <&cpucp_scp_lpri1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_vendor: protocol@80 {
+ reg = <0x80>;
+ };
+ };
+
scmi {
compatible = "arm,scmi";
mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>;
@@ -5675,6 +5690,13 @@ pdp0_mbox: mailbox@17610000 {
#mbox-cells = <1>;
};
+ cpucp_mbox: mailbox@17620000 {
+ compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
+ reg = <0 0x17620000 0 0x8000>, <0 0x18830000 0 0x8000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ };
+
timer@17810000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x17810000 0x0 0x1000>;
@@ -5859,6 +5881,26 @@ rpmhpd_opp_turbo_l1: opp-416 {
};
};
+ cpucp_sram: sram@18b4e000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x18b4e000 0x0 0x400>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0x0 0x0 0x18b4e000 0x400>;
+
+ cpucp_scp_lpri0: scp-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x200>;
+ };
+
+ cpucp_scp_lpri1: scp-sram-section@200 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x200 0x200>;
+ };
+ };
+
nsi_noc: interconnect@1d600000 {
compatible = "qcom,glymur-nsinoc";
reg = <0x0 0x1d600000 0x0 0x14080>;
On Qualcomm Glymur SoCs, the memlat governor and the mechanism to control the LLCC and DDR/DDR_QOS is hosted on the CPU Control Processor (CPUCP). Enable the nodes required to get QCOM SCMI Generic Extension protocol to probe on Glymur and Mahua SoCs. Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/glymur.dtsi | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+)