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Thu, 11 Dec 2025 22:08:08 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 11 Dec 2025 22:08:07 -0800 Received: from build-amhetre-focal-20250825.internal (10.127.8.10) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Thu, 11 Dec 2025 22:08:07 -0800 From: Ashish Mhetre To: , , , , , , CC: , , , , , , , , , Ashish Mhetre Subject: [PATCH V6 4/4] arm64: dts: nvidia: Add nodes for CMDQV Date: Fri, 12 Dec 2025 06:08:03 +0000 Message-ID: <20251212060803.1712637-5-amhetre@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251212060803.1712637-1-amhetre@nvidia.com> References: <20251212060803.1712637-1-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002314:EE_|IA1PR12MB6577:EE_ X-MS-Office365-Filtering-Correlation-Id: 8c66b27b-f7d0-4671-b851-08de3944db05 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700013; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2025 06:08:22.7013 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8c66b27b-f7d0-4671-b851-08de3944db05 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002314.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6577 The Command Queue Virtualization (CMDQV) hardware is part of the SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in virtualizing the command queue for the SMMU. Update SMMU compatible strings to use nvidia,tegra264-smmu to enable CMDQV support. Add device tree nodes for the CMDQV hardware and enable them on the tegra264-p3834 platform where SMMUs are enabled. Each SMMU instance is paired with its corresponding CMDQV instance via the nvidia,cmdqv property. Signed-off-by: Ashish Mhetre --- .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 8 +++ arch/arm64/boot/dts/nvidia/tegra264.dtsi | 50 +++++++++++++++++-- 2 files changed, 53 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi index 06795c82427a..7e2c3e66c2ab 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi @@ -23,8 +23,16 @@ iommu@5000000 { status = "okay"; }; + cmdqv@5200000 { + status = "okay"; + }; + iommu@6000000 { status = "okay"; }; + + cmdqv@6200000 { + status = "okay"; + }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index f137565da804..9eb7058e3149 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3361,7 +3361,7 @@ bus@8100000000 { <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */ smmu1: iommu@5000000 { - compatible = "arm,smmu-v3"; + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; reg = <0x00 0x5000000 0x0 0x200000>; interrupts = , ; @@ -3370,10 +3370,18 @@ smmu1: iommu@5000000 { #iommu-cells = <1>; dma-coherent; + nvidia,cmdqv = <&cmdqv1>; + }; + + cmdqv1: cmdqv@5200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x00 0x5200000 0x0 0x830000>; + interrupts = ; + status = "disabled"; }; smmu2: iommu@6000000 { - compatible = "arm,smmu-v3"; + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; reg = <0x00 0x6000000 0x0 0x200000>; interrupts = , ; @@ -3382,6 +3390,14 @@ smmu2: iommu@6000000 { #iommu-cells = <1>; dma-coherent; + nvidia,cmdqv = <&cmdqv2>; + }; + + cmdqv2: cmdqv@6200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x00 0x6200000 0x0 0x830000>; + interrupts = ; + status = "disabled"; }; mc: memory-controller@8020000 { @@ -3437,7 +3453,7 @@ emc: external-memory-controller@8800000 { }; smmu0: iommu@a000000 { - compatible = "arm,smmu-v3"; + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; reg = <0x00 0xa000000 0x0 0x200000>; interrupts = , ; @@ -3446,10 +3462,18 @@ smmu0: iommu@a000000 { #iommu-cells = <1>; dma-coherent; + nvidia,cmdqv = <&cmdqv0>; + }; + + cmdqv0: cmdqv@a200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x00 0xa200000 0x0 0x830000>; + interrupts = ; + status = "disabled"; }; smmu4: iommu@b000000 { - compatible = "arm,smmu-v3"; + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; reg = <0x00 0xb000000 0x0 0x200000>; interrupts = , ; @@ -3458,6 +3482,14 @@ smmu4: iommu@b000000 { #iommu-cells = <1>; dma-coherent; + nvidia,cmdqv = <&cmdqv4>; + }; + + cmdqv4: cmdqv@b200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x00 0xb200000 0x0 0x830000>; + interrupts = ; + status = "disabled"; }; i2c14: i2c@c410000 { @@ -3690,7 +3722,7 @@ bus@8800000000 { ranges = <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>; smmu3: iommu@6000000 { - compatible = "arm,smmu-v3"; + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; reg = <0x00 0x6000000 0x0 0x200000>; interrupts = , ; @@ -3699,6 +3731,14 @@ smmu3: iommu@6000000 { #iommu-cells = <1>; dma-coherent; + nvidia,cmdqv = <&cmdqv3>; + }; + + cmdqv3: cmdqv@6200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x00 0x6200000 0x0 0x830000>; + interrupts = ; + status = "disabled"; }; hda@90b0000 {