@@ -26,5 +26,13 @@ iommu@5000000 {
iommu@6000000 {
status = "okay";
};
+
+ cmdqv@5200000 {
+ status = "okay";
+ };
+
+ cmdqv@6200000 {
+ status = "okay";
+ };
};
};
@@ -212,6 +212,7 @@ smmu1: iommu@5000000 {
#iommu-cells = <1>;
dma-coherent;
+ nvidia,cmdqv = <&cmdqv1>;
};
smmu2: iommu@6000000 {
@@ -224,6 +225,25 @@ smmu2: iommu@6000000 {
#iommu-cells = <1>;
dma-coherent;
+ nvidia,cmdqv = <&cmdqv2>;
+ };
+
+ cmdqv1: cmdqv@5200000 {
+ compatible = "nvidia,tegra264-cmdqv";
+ status = "disabled";
+
+ reg = <0x00 0x5200000 0x0 0x830000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmdqv";
+ };
+
+ cmdqv2: cmdqv@6200000 {
+ compatible = "nvidia,tegra264-cmdqv";
+ status = "disabled";
+
+ reg = <0x00 0x6200000 0x0 0x830000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmdqv";
};
mc: memory-controller@8020000 {
@@ -288,6 +308,7 @@ smmu0: iommu@a000000 {
#iommu-cells = <1>;
dma-coherent;
+ nvidia,cmdqv = <&cmdqv0>;
};
smmu4: iommu@b000000 {
@@ -300,6 +321,25 @@ smmu4: iommu@b000000 {
#iommu-cells = <1>;
dma-coherent;
+ nvidia,cmdqv = <&cmdqv4>;
+ };
+
+ cmdqv0: cmdqv@a200000 {
+ compatible = "nvidia,tegra264-cmdqv";
+ status = "disabled";
+
+ reg = <0x00 0xa200000 0x0 0x830000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmdqv";
+ };
+
+ cmdqv4: cmdqv@b200000 {
+ compatible = "nvidia,tegra264-cmdqv";
+ status = "disabled";
+
+ reg = <0x00 0xb200000 0x0 0x830000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmdqv";
};
i2c14: i2c@c410000 {
@@ -541,6 +581,16 @@ smmu3: iommu@6000000 {
#iommu-cells = <1>;
dma-coherent;
+ nvidia,cmdqv = <&cmdqv3>;
+ };
+
+ cmdqv3: cmdqv@6200000 {
+ compatible = "nvidia,tegra264-cmdqv";
+ status = "disabled";
+
+ reg = <0x00 0x6200000 0x0 0x830000>;
+ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmdqv";
};
};
The Command Queue Virtualization (CMDQV) hardware is part of the SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in virtualizing the command queue for the SMMU. Add device tree nodes for the CMDQV hardware in the Tegra264 SoC device tree and enable them on the tegra264-p3834 platform where SMMUs are enabled. Each SMMU instance is paired with its corresponding CMDQV instance via the nvidia,cmdqv property. Signed-off-by: Ashish Mhetre <amhetre@nvidia.com> --- .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 8 +++ arch/arm64/boot/dts/nvidia/tegra264.dtsi | 50 +++++++++++++++++++ 2 files changed, 58 insertions(+)