| Message ID | 20251026231859.823231-1-alex.t.tran@gmail.com |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | [v1] clk: tegra: clk-dfll: scale force_val with coefficient according to whether cg_scale is set | expand |
On Monday, October 27, 2025 8:18 AM Alex Tran wrote: > force_val was hard coded to use a coefficient of 128, > regardless of the cg_scale configuration. This should instead match the > DFLL_PARAMS_CG_SCALE bit, use a coefficient of 128 when > cg_scale is set, or 1 when not set. > > Signed-off-by: Alex Tran <alex.t.tran@gmail.com> > --- > drivers/clk/tegra/clk-dfll.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c > index 22dc29432eff..3362983eedcf 100644 > --- a/drivers/clk/tegra/clk-dfll.c > +++ b/drivers/clk/tegra/clk-dfll.c > @@ -882,7 +882,7 @@ static void dfll_set_frequency_request(struct tegra_dfll *td, > { > u32 val = 0; > int force_val; > - int coef = 128; /* FIXME: td->cg_scale? */ > + int coef = td->cg_scale ? 128 : 1; > > force_val = (req->lut_index - td->lut_safe) * coef / td->cg; > force_val = clamp(force_val, FORCE_MIN, FORCE_MAX); > Are you seeing some concrete issue that this is fixing? While the current code indeed doesn't look correct, it matches what the downstream kernels do. A quick grep doesn't find any device trees that set 'nvidia,cg-scale', so this patch would change the behavior from 128 to 1, and no longer be aligned with downstream releases. Mikko
diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c index 22dc29432eff..3362983eedcf 100644 --- a/drivers/clk/tegra/clk-dfll.c +++ b/drivers/clk/tegra/clk-dfll.c @@ -882,7 +882,7 @@ static void dfll_set_frequency_request(struct tegra_dfll *td, { u32 val = 0; int force_val; - int coef = 128; /* FIXME: td->cg_scale? */ + int coef = td->cg_scale ? 128 : 1; force_val = (req->lut_index - td->lut_safe) * coef / td->cg; force_val = clamp(force_val, FORCE_MIN, FORCE_MAX);
force_val was hard coded to use a coefficient of 128, regardless of the cg_scale configuration. This should instead match the DFLL_PARAMS_CG_SCALE bit, use a coefficient of 128 when cg_scale is set, or 1 when not set. Signed-off-by: Alex Tran <alex.t.tran@gmail.com> --- drivers/clk/tegra/clk-dfll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)