| Message ID | 20250512050010.1025259-2-sheetal@nvidia.com |
|---|---|
| State | New |
| Headers | show
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Sun, 11 May 2025 22:00:33 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Sun, 11 May 2025 22:00:32 -0700 Received: from build-sheetal-bionic-20250305.nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Sun, 11 May 2025 22:00:32 -0700 From: "Sheetal ." <sheetal@nvidia.com> To: <vkoul@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org> CC: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <ldewangan@nvidia.com>, <dmaengine@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Sheetal <sheetal@nvidia.com> Subject: [PATCH v2 1/2] dt-bindings: Document Tegra264 ADMA support Date: Mon, 12 May 2025 05:00:09 +0000 Message-ID: <20250512050010.1025259-2-sheetal@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250512050010.1025259-1-sheetal@nvidia.com> References: <20250512050010.1025259-1-sheetal@nvidia.com> Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: <linux-tegra.vger.kernel.org> List-Subscribe: <mailto:linux-tegra+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-tegra+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003448:EE_|SN7PR12MB7228:EE_ X-MS-Office365-Filtering-Correlation-Id: 2fddbbda-6b38-4c56-77d4-08dd9111f4a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; 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Add Tegra264 support in ADMA driver
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expand
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On Mon, May 12, 2025 at 05:00:09AM +0000, Sheetal . wrote: > From: Sheetal <sheetal@nvidia.com> > > Add Tegra264 ADMA support to the device tree bindings documentation. > The Tegra264 ADMA hardware supports 64 DMA channels and requires > specific register configurations. > > Signed-off-by: Sheetal <sheetal@nvidia.com> Acked-by: Conor Dooley <conor.dooley@microchip.com>
diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index d3f8c269916c..da0235e451d6 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -19,6 +19,7 @@ properties: - enum: - nvidia,tegra210-adma - nvidia,tegra186-adma + - nvidia,tegra264-adma - items: - enum: - nvidia,tegra234-adma @@ -92,6 +93,7 @@ allOf: contains: enum: - nvidia,tegra186-adma + - nvidia,tegra264-adma then: anyOf: - properties: